View M58WR016KL60ZA6U_6850512.PDF datasheet online --- IC-ON-LINE

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december 2007 rev 2 1/123 1 m58wr016ku m58wr016kl m58wr032ku m58wr032kl m58wr064ku m58wr064kl 16-, 32- and 64-mbit (x 16, mux i/o, multiple bank, burst) 1.8 v supply flash memories features supply voltage ?v dd = 1.7 v to 2 v for program, erase and read ?v ddq = 1.7 v to 2 v for i/o buffers ?v pp = 9 v for fast program multiplexed address/data synchronous / asynchronous read ? synchronous burst read mode: 86 mhz ? random access: 60 ns, 70 ns synchronous burst read suspend programming time ? 10 s by word typical for factory program ? double/quadruple word program option ? enhanced factory program options memory blocks ? multiple bank memory array: 4 mbit banks ? parameter blocks (top or bottom location) dual operations ? program erase in one bank while read in others ? no delay between read and write operations block locking ? all blocks locked at power up ? any combination of blocks can be locked ?wp for block lock-down security ? 128 bit user programmable otp cells ? 64 bit unique device number common flash interface (cfi) 100,000 program/erase cycles per block electronic signature ? manufacturer code: 20h ? top device code, m58wr016ku: 8823h m58wr032ku: 8828h m58wr064ku: 88c0h ? bottom device code, m58wr016kl: 8824h m58wr032kl: 8829h m58wr064kl: 88c1h ecopack? packages available vfbga44 (za) 7.5 5 mm fbga www.numonyx.com
contents m58wrxxxku, m58wrxxxkl 2/123 contents 1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2 signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.1 address inputs (adq0-adq15, a16-amax) . . . . . . . . . . . . . . . . . . . . . . . 17 2.2 data input/output (adq0-adq15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.3 chip enable (e ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.4 output enable (g ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.5 write enable (w ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.6 write protect (wp ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.7 reset/power-down (rp ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.8 latch enable (l ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.9 clock (k) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.10 wait (wait) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.11 bus invert (binv) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.12 v dd supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.13 v ddq supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.14 v pp program supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.15 v ss ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.16 v ssq ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3 bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.1 bus read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.2 bus write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.3 address latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.4 output disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.5 standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.6 reset/power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4 command interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5 command interface - standard commands . . . . . . . . . . . . . . . . . . . . . 23 5.1 read array command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
m58wrxxxku, m58wrxxxkl contents 3/123 5.2 read status register command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.3 read electronic signature command . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.4 read cfi query command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.5 clear status register command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.6 block erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.7 program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.8 program/erase suspend command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.9 program/erase resume command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.10 protection register program command . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.11 set configuration register command . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.12 block lock command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.13 block unlock command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.14 block lock-down command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6 command interface - factory program co mmands . . . . . . . . . . . . . . . 31 6.1 double word program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.2 quadruple word program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.3 enhanced factory program command . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6.3.1 setup phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6.3.2 program phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6.3.3 verify phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6.3.4 exit phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6.4 quadruple enhanced factory program command . . . . . . . . . . . . . . . . . . 35 6.4.1 setup phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 6.4.2 load phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 6.4.3 program and verify phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6.4.4 exit phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7 status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7.1 program/erase controller status bit (sr7) . . . . . . . . . . . . . . . . . . . . . . . 38 7.2 erase suspend status bit (sr6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7.3 erase status bit (sr5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 7.4 program status bit (sr4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 7.5 v pp status bit (sr3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 7.6 program suspend status bit (sr2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
contents m58wrxxxku, m58wrxxxkl 4/123 7.7 block protection status bit (sr1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 7.8 bank write/multiple word program status bit (sr0) . . . . . . . . . . . . . . . . 40 8 configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 8.1 read select bit (cr15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 8.2 bus invert configuration (cr14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 8.3 x-latency bits (cr13-cr11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 8.4 wait polarity bit (cr10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 8.5 data output configuration bit (cr9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 8.6 wait configuration bit (cr8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 8.7 burst type bit (cr7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 8.8 valid clock edge bit (cr6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 8.9 power-down bit (cr5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 8.10 wrap burst bit (cr3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 8.11 burst length bits (cr2-cr0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 9 read modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 9.1 asynchronous read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 9.2 synchronous burst read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 9.2.1 synchronous burst read suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 9.3 single synchronous read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 10 dual operations and multiple bank architectu re . . . . . . . . . . . . . . . . . 54 11 block locking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 11.1 reading a block?s lock status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 11.2 locked state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 11.3 unlocked state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 11.4 lock-down state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 11.5 locking operations during erase suspend . . . . . . . . . . . . . . . . . . . . . . . . 57 12 program and erase times and endurance cycles . . . . . . . . . . . . . . . . . 59 13 maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
m58wrxxxku, m58wrxxxkl contents 5/123 14 dc and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 15 package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 16 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 appendix a block address tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 appendix b common flash interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 appendix c flowcharts and pseudocodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 16.1 enhanced factory program pseudocode . . . . . . . . . . . . . . . . . . . . . . . . 114 16.2 quadruple enhanced factory program pseu docode . . . . . . . . . . . . . . . . 116 appendix d command interface state ta bles. . . . . . . . . . . . . . . . . . . . . . . . . . . 117 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
list of tables m58wrxxxku, m58wrxxxkl 6/123 list of tables table 1. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 2. m58wr016ku/l bank architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 3. m58wr032ku/l bank architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 4. m58wr064ku/l bank architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 5. bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 6. command codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 7. standard commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 8. electronic signature codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 9. factory program commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 7 table 10. status register bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 11. x-latency settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 12. configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 13. burst type definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 14. dual operations allowed in other banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4 table 15. dual operations allowed in same bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 16. dual operation limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 17. lock status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 table 18. program, erase times and endurance cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 table 19. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 20. operating and ac measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 table 21. capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 table 22. dc characteristics - currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 table 23. dc characteristics - voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 table 24. asynchronous read ac characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 table 25. synchronous read ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 table 26. write ac characteristics, write enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 table 27. write ac characteristics, chip enable controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 table 28. reset and power-up ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 table 29. vfbga44 7.5 5 mm, 10 4 ball array, 0.50 mm pitch, package mechanical data . . . . . 77 table 30. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 table 31. top boot block addresses, m58wr016ku. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 table 32. bottom boot block addresses, m58wr016kl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 table 33. top boot block addresses, m58wr032ku. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 table 34. bottom boot block addresses, m58wr032kl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 table 35. top boot block addresses, m58wr064ku. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 table 36. bottom boot block addresses, m58wr064kl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 table 37. query structure overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 table 38. cfi query identification string . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 table 39. cfi query system interface information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 7 table 40. device geometry definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 table 41. primary algorithm-specific extended query table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 table 42. protection register information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 table 43. burst read information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 table 44. bank and erase block region information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 table 45. bank and erase block region 1 information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 table 46. bank and erase block region 2 information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 table 47. command interface states - modify table, next state . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 table 48. command interface states - modify table, next output . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
m58wrxxxku, m58wrxxxkl list of tables 7/123 table 49. command interface states - lock table, next state. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 table 50. command interface states - lock table, next output . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 table 51. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
list of figures m58wrxxxku, m58wrxxxkl 8/123 list of figures figure 1. logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 2. vfbga44 connections (top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 3. m58wr016ku/l memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 4. m58wr032ku/l memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 5. m58wr064ku/l memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 6. protection register memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 7. x-latency and data output configuration example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 figure 8. wait configuration example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 figure 9. ac measurement i/o waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1 figure 10. ac measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 figure 11. asynchronous random access read ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 figure 12. synchronous burst read ac waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 figure 13. single synchronous read ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 figure 14. synchronous burst read suspend ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 figure 15. clock input ac waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 figure 16. write ac waveforms, write enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 figure 17. write ac waveforms, chip enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 figure 18. reset and power-up ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 5 figure 19. vfbga44 7.5 5 mm, 10 4 ball array, 0.50 mm pitch, bottom view package outline . . 76 figure 20. program flowchart and pseudocode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 figure 21. double word program flowchart and pseudocode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 figure 22. quadruple word program flowchart and pseudocode . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 figure 23. program suspend & resume flowchart and pseudocode . . . . . . . . . . . . . . . . . . . . . . . . 108 figure 24. block erase flowchart and pseudocode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 figure 25. erase suspend & resume flowchart and pseudocode . . . . . . . . . . . . . . . . . . . . . . . . . . 110 figure 26. locking operations flowchart and pseudocode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 figure 27. protection register program flowchart and pseudocode . . . . . . . . . . . . . . . . . . . . . . . . . 112 figure 28. enhanced factory program flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 figure 29. quadruple enhanced factory program flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
m58wrxxxku, m58wrxxxkl description 9/123 1 description the m58wr016ku/l, m58wr032ku/l and m58wr064ku/l are 16-mbit (1 mbit 16), 32- mbit (2 mbit 16) and 64-mbit (4 mbit 16) non-volatile flash memories, respectively. in the rest of the document, they will be referred to as m58wrxxxku/l unless otherwise specified. the m58wrxxxku/l may be erased electrically at block level and programmed in-system on a word-by-word basis using a 1.7 v to 2 v v dd supply for the circuitry and a 1.7 v to 2 v v ddq supply for the input/output pins. an optional 9 v v pp power supply is provided to speed up customer programming. the first sixteen address lines are multiplexed with the data input/output signals on the multiplexed address/data bus adq0-adq15. the remaining address lines, a16-amax, are the most significant bit addresses. the device features an asymmetrical block architecture: the m58wr016ku/l have an array of 39 blocks, and are divided into 4 mbit banks. there are 3 banks each containing 8 main blocks of 32 kwords, and one parameter bank containing 8 parameter blocks of 4 kwords and 7 main blocks of 32 kwords. the m58wr032ku/l have an array of 71 blocks, and are divided into 4 mbit banks. there are 7 banks each containing 8 main blocks of 32 kwords, and one parameter bank containing 8 parameter blocks of 4 kwords and 7 main blocks of 32 kwords. the m58wr064ku/l have an array of 135 blocks, and are divided into 4 mbit banks. there are 15 banks each containing 8 main blocks of 32 kwords, and one parameter bank containing 8 parameter blocks of 4 kwords and 7 main blocks of 32 kwords. the multiple bank architecture allows dual operations, while programming or erasing in one bank, read operations are possible in other banks. only one bank at a time is allowed to be in program or erase mode. it is possible to perform burst reads that cross bank boundaries. the bank architectures are summarized in tables 2 , 3 and 4 , and the memory maps are shown in figures 3 , 4 and 5 . the parameter blocks are located at the top of the memory address space for the m58wr016ku, m58wr032ku and m58wr064ku, and at the bottom for the m58wr016kl, m58wr032kl and m58wr064kl. each block can be erased separately. erase can be suspended, in order to perform program in any other block, and then resumed. program can be suspended to read data in any other block and then resumed. each block can be programmed and erased over 100,000 cycles using the supply voltage v dd . there are two enhanced factory programming commands available to speed up programming. program and erase commands are written to the command interface of the memory. an internal program/erase controller takes care of the timings necessary for program and erase operations. the end of a program or erase operation can be detected and any error conditions identified in the status register. the command set required to control the memory is consistent with jedec standards. the device supports synchronous burst read and asynchronous read from all blocks of the memory array; at power-up the device is configured for asynchronous read. in synchronous burst mode, data is output on each clock cycle at frequencies of up to 86 mhz. the synchronous burst read operation can be suspended and resumed.
description m58wrxxxku, m58wrxxxkl 10/123 the device features an automatic standby mode. when the bus is inactive during asynchronous read operations, the device autom atically switches to the automatic standby mode. in this condition the power consumption is reduced to the standby value i dd4 and the outputs are still driven. the m58wrxxxku/l features an in stant, individual block locking scheme that allows any block to be locked or unlocked with no latency, enabling instant code and data protection. all blocks have three levels of protection. they can be locked and locked-down individually preventing any accidental programming or erasure. there is an additional hardware protection against program and erase. when v pp v pplk all blocks are protected against program or erase. all blocks are locked at power- up. the device includes a protection register to increase the protection of a system?s design. the protection register is divided into two segments: a 64 bit segment containing a unique device number written by numonyx, and a 128 bit segment one-time-programmable (otp) by the user. the user programmable segment can be permanently protected. figure 6 , shows the protection register memory map. the memory is available in a vfbga44 7.5 5 mm, 10 4 active ball array, 0.5 mm pitch package. it is supplied with all the bits erased (set to ?1?).
m58wrxxxku, m58wrxxxkl description 11/123 figure 1. logic diagram 1. amax is equal to a19 in the m58wr016ku/l, to a20 in the m58wr032ku/l, and to a21 in the m58wr064ku/l. w adq0-adq15 v dd e v ss 16 g rp wp v ddq v pp l k wait binv ai13519 a16-amax (1) m58wr016ku m58wr016kl m58wr032ku m58wr032kl m58wr064ku m58wr064kl v ssq table 1. signal names name description direction a16-amax (1) address inputs inputs adq0-adq15 data input/outputs or address inputs, command inputs i/o e chip enable input g output enable input w write enable input rp reset/power-down input wp write protect input k clock input l latch enable input wait wait output binv bus invert i/o v dd supply voltage v ddq supply voltage for input/output buffers v pp optional supply voltage for fast program & erase v ss ground v ssq ground input/output supply nc not connected internally 1. amax is equal to a19 in the m58wr016ku/l, to a20 in the m58wr032ku/l, and to a21 in the m58wr064ku/l.
description m58wrxxxku, m58wrxxxkl 12/123 figure 2. vfbga44 connections (top view through package) ai13520 v ddq adq10 adq11 adq4 adq5 v ssq adq14 adq15 h adq9 adq2 adq3 adq6 adq7 v ss g a18 wp rp binv l a20/ nc (1) a16 v ddq f a19 v pp w v dd k wait e 8 7 6 5 4 3 2 1 adq1 adq8 e a17 adq0 g 10 9 adq13 adq12 v ss v ssq d c b a nc nc 12 11 nc nc 14 13 a21/ nc (1) nc note1: ball d5 is a20 in the m58wr032ku/l and m58wr064ku/l, it is not connected internally (nc) in the m58wr016ku/l. ball c4 is a21 in the m58wr064ku/l, it is not connected internally (nc) in the m58wr016ku/l and m58wr032ku/l.
m58wrxxxku, m58wrxxxkl description 13/123 table 2. m58wr016ku/l bank architecture number bank size parameter blocks main blocks parameter bank 4 mbit 8 blocks of 4 kword 7 blocks of 32 kword bank 1 4 mbit - 8 blocks of 32 kword bank 2 4 mbit - 8 blocks of 32 kword bank 3 4 mbit - 8 blocks of 32 kword table 3. m58wr032ku/l bank architecture number bank size parameter blocks main blocks parameter bank 4 mbit 8 blocks of 4 kword 7 blocks of 32 kword bank 1 4 mbit - 8 blocks of 32 kword bank 2 4 mbit - 8 blocks of 32 kword bank 3 4 mbit - 8 blocks of 32 kword ---- ---- ---- ---- bank 6 4 mbit - 8 blocks of 32 kword bank 7 4 mbit - 8 blocks of 32 kword table 4. m58wr064ku/l bank architecture number bank size parameter blocks main blocks parameter bank 4 mbit 8 blocks of 4 kword 7 blocks of 32 kword bank 1 4 mbit - 8 blocks of 32 kword bank 2 4 mbit - 8 blocks of 32 kword bank 3 4 mbit - 8 blocks of 32 kword ---- ---- ---- ---- bank 14 4 mbit - 8 blocks of 32 kword bank 15 4 mbit - 8 blocks of 32 kword
description m58wrxxxku, m58wrxxxkl 14/123 figure 3. m58wr016ku/l memory map ai13521 m58wr016ku - top boot block address lines adq0-adq15 and a16-a19 8 main blocks bank 3 m58wr016kl - bottom boot block address lines adq0-adq15 and a16-a19 32 kword 00000h 07fffh 32 kword 38000h 3ffffh 32 kword 40000h 47fffh 32 kword 78000h 7ffffh 32 kword 80000h 87fffh 32 kword b8000h bffffh 32 kword c0000h c7fffh 32 kword f0000h f7fffh 4 kword f8000h f8fffh 4 kword ff000h fffffh 8 parameter blocks parameter bank parameter bank 4 kword 00000h 00fffh 4kword 07000h 07fffh 32 kword 08000h 0ffffh 32 kword 38000h 3ffffh 32 kword 40000h 47fffh 32 kword 78000h 7ffffh 32 kword 80000h 87fffh 32 kword b8000h bffffh 32 kword c0000h c7fffh 32 kword f8000h fffffh bank 2 bank 1 bank 3 bank 2 bank 1 8 main blocks 8 main blocks 7 main blocks 8 parameter blocks 7 main blocks 8 main blocks 8 main blocks 8 main blocks
m58wrxxxku, m58wrxxxkl description 15/123 figure 4. m58wr032ku/l memory map ai10158 m58wr032ku - top boot block address lines a20-a16 and adq15-adq0 8 main blocks bank 7 m58wr032kl - bottom boot block address lines a20-a16 and adq15-adq0 32 kword 000000h 007fffh 32 kword 038000h 03ffffh 32 kword 100000h 107fffh 32 kword 138000h 13ffffh 32 kword 140000h 147fffh 32 kword 178000h 17ffffh 32 kword 180000h 187fffh 32 kword 1b8000h 1bffffh 32 kword 1c0000h 1c7fffh 32 kword 1f0000h 1f7fffh 4 kword 1f8000h 1f8fffh 4 kword 1ff000h 1fffffh 8 parameter blocks parameter bank parameter bank 4 kword 000000h 000fffh 4kword 007000h 007fffh 32 kword 008000h 00ffffh 32 kword 038000h 03ffffh 32 kword 040000h 047fffh 32 kword 078000h 07ffffh 32 kword 080000h 087fffh 32 kword 0b8000h 0bffffh 32 kword 0c0000h 0c7fffh 32 kword 0f8000h 0fffffh 32 kword 1c0000h 1c7fffh 32 kword 1f8000h 1fffffh bank 3 bank 2 bank 1 bank 7 bank 3 bank 2 bank 1 8 main blocks 8 main blocks 8 main blocks 7 main blocks 8 parameter blocks 7 main blocks 8 main blocks 8 main blocks 8 main blocks 8 main blocks
description m58wrxxxku, m58wrxxxkl 16/123 figure 5. m58wr064ku/l memory map ai13456 m58wr064ku - top boot block address lines a21-a16 and adq15-adq0 8 main blocks bank 15 m58wr064kl - bottom boot block address lines a21-a16 and adq15-adq0 32 kword 000000h 007fffh 32 kword 038000h 03ffffh 32 kword 300000h 307fffh 32 kword 338000h 33ffffh 32 kword 340000h 347fffh 32 kword 378000h 37ffffh 32 kword 380000h 387fffh 32 kword 3b8000h 3bffffh 32 kword 3c0000h 3c7fffh 32 kword 3f0000h 3f7fffh 4 kword 3f8000h 3f8fffh 4 kword 3ff000h 3fffffh 8 parameter blocks parameter bank parameter bank 4 kword 000000h 000fffh 4kword 007000h 007fffh 32 kword 008000h 00ffffh 32 kword 038000h 03ffffh 32 kword 040000h 047fffh 32 kword 078000h 07ffffh 32 kword 080000h 087fffh 32 kword 0b8000h 0bffffh 32 kword 0c0000h 0c7fffh 32 kword 0f8000h 0fffffh 32 kword 3c0000h 3c7fffh 32 kword 3f8000h 3fffffh bank 3 bank 2 bank 1 bank 15 bank 3 bank 2 bank 1 8 main blocks 8 main blocks 8 main blocks 7 main blocks 8 parameter blocks 7 main blocks 8 main blocks 8 main blocks 8 main blocks 8 main blocks
m58wrxxxku, m58wrxxxkl signal descriptions 17/123 2 signal descriptions see figure 1: logic diagram and table 1: signal names , for a brief overview of the signals connected to this device. 2.1 address inputs (adq0-adq15, a16-amax) amax is equal to a19 in the m58wr016ku/l, to a20 in the m58wr032ku/l, and to a21 in the m58wr064ku/l. the address inputs select the cells in the memory array to access during bus read operations. during bus write operations they control the commands sent to the command interface of the program/erase controller. 2.2 data input/output (adq0-adq15) the data i/o outputs the data stored at the selected address during a bus read operation or inputs a command or the data to be programmed during a bus write operation. 2.3 chip enable (e ) the chip enable input activates the memory control logic, input buffers, decoders and sense amplifiers. when chip enable is at v il and reset is at v ih the device is in active mode. when chip enable is at v ih the memory is deselected, the outputs are high impedance and the power consumption is reduced to the standby level. 2.4 output enable (g ) the output enable controls data outputs during the bus read operation of the memory. 2.5 write enable (w ) the write enable controls the bus write operation of the memory?s command interface. the data is latched on the rising edge of chip enable or write enable whichever occurs first. 2.6 write protect (wp ) write protect is an input that gives an additional hardware protection for each block. when write protect is at v il , the lock-down is enabled and the protection status of the locked- down blocks cannot be changed. when write protect is at v ih , the lock-down is disabled and the locked-down blocks can be locked or unlocked. (refer to table 17: lock status ).
signal descriptions m58wrxxxku, m58wrxxxkl 18/123 2.7 reset/power-down (rp ) the reset/power-down input provides a hardware reset of the memory, and/or power-down functions, depending on the settings in the configuration register. when reset/power- down is at v il , the memory is in reset mode: the outputs are high impedance and the current consumption is reduced to the standby supply current i dd3 , or to the reset/power- down supply current i dd2 if the power-down function is enabled. refer to ta b l e 2 2 : d c characteristics - currents , for the value of i dd2 and i dd3 . after reset all blocks are in the locked state and the bits of the configuration register are reset except for power-down bit cr5. when reset/power-down is at v ih , the device is in normal operation. exiting reset mode the device enters asynchronous read mode, but a negative transition of chip enable or latch enable is required to ensure valid data outputs. 2.8 latch enable (l ) latch enable latches the adq0-adq15 and a16-amax address bits on its rising edge. the address latch is transparent when latch enable is at v il and it is inhibited when latch enable is at v ih . 2.9 clock (k) the clock input synchronizes the memory to the microcontroller during synchronous read operations; the address is latched on a clock edge (rising or falling, according to the configuration settings) when latch enable is at v il . clock is don't care during asynchronous read and in write operations. 2.10 wait (wait) wait is an output signal used during synchronous read to indicate whether the data on the output bus are valid. this output is high impedance when chip enable is at v ih or reset is at v il . it can be configured to be active during the wait cycle or one clock cycle in advance. the wait signal is forced deasserted when output enable is at v ih . 2.11 bus invert (binv) bus invert is an input/output signal used to reduce the amount of power required to switch the external address/data bus. power is saved by inverting the data on adq0-adq15 each time the inversion results in a reduced number of pin transitions. data is inverted when binv is at v ih (i.e. if the data is aaaah and binv is at v ih , aaaah becomes 5555h) . binv is high impedance when chip enable or output enable is at v ih or when reset/po wer down is at v il . 2.12 v dd supply voltage v dd provides the power supply to the internal core of the memory device. it is the main power supply for all operations (read, program and erase).
m58wrxxxku, m58wrxxxkl signal descriptions 19/123 2.13 v ddq supply voltage v ddq provides the power supply to the i/o pins and enables all outputs to be powered independently from v dd . v ddq can be tied to v dd or can use a separate supply. 2.14 v pp program supply voltage v pp is both a control input and a power supply pin. the two functions are selected by the voltage range applied to the pin. if v pp is kept in a low voltage range (0 v to v ddq ) v pp is seen as a control input. in this case a voltage lower than v pplk gives an absolute protection against program or erase, while v pp in the v pp1 range enables these functions (see tables 22 and 23 , dc characteristics for the relevant values). v pp is only sampled at the beginning of a program or erase; a change in its value after the operation has started does not have any effect and program or erase operations continue. if v pp is in the range of v pph it acts as a power supply pin. in this condition v pp must be stable until the program/erase algorithm is completed. 2.15 v ss ground v ss ground is the reference for the core supply. it must be connected to the system ground. 2.16 v ssq ground v ssq ground is the reference for the input/output circuitry driven by v ddq . v ssq must be connected to v ss . note: each device in a system should have v dd , v ddq and v pp decoupled with a 0.1 f ceramic capacitor close to the pin (high fre quency, inherently low inductance capacitors should be as close as possible to the package). see figure 10: ac measurement load circuit . the pcb track widths should be sufficient to carry the required v pp program and erase currents.
bus operations m58wrxxxku, m58wrxxxkl 20/123 3 bus operations there are six standard bus operations that control the device. these are bus read, bus write, address latch, output disable, standby and reset. see table 5: bus operations , for a summary. typically glitches of less than 5ns on chip enable or write enable are ignored by the memory and do not affect bus write operations. 3.1 bus read bus read operations are used to output the contents of the memory array, the electronic signature, the status register and the common flash interface. both chip enable and output enable must be at v il in order to perform a read operation. the chip enable input should be used to enable the device. output enable should be used to gate data onto the output. the data read depends on the previous command written to the memory (see command interface section). see figures 11 , 12 and 13 read ac waveforms, and tables 24 and 25 read ac characteristics, for details of when the output becomes valid. 3.2 bus write bus write operations write commands to the memory or latch input data to be programmed. a bus write operatio n is initiated when chip enable and write enable are at v il with output enable at v ih . commands and input data are latched on the rising edge of write enable or chip enable, whichever occurs first. the addresses must also be latched prior to the write operation by toggling la tch enable (when chip enable is at v il ). the latch enable must be tied to v ih during the bus write operation. see figures 16 and 17 , write ac waveforms, and tables 26 and 27 , write ac characteristics, for details of the timing requirements. 3.3 address latch address latch operations input valid addresses. both chip enable and latch enable must be at v il during address latch operations. the addresses are latched on the rising edge of latch enable. 3.4 output disable the outputs are high impedance when the output enable is at v ih .
m58wrxxxku, m58wrxxxkl bus operations 21/123 3.5 standby standby disables most of the internal circuitry allowing a substantial reduction of the current consumption. the memory is in standby when chip enable and reset are at v ih . the power consumption is reduced to the standby level and the outputs are set to high impedance, independently from the output enable or write enable inputs. if chip enable switches to v ih during a program or erase operation, the device enters standby mode when finished. 3.6 reset/power-down during reset mode the memory is deselected and the outputs are high impedance. the memory is in reset mode when reset/power-down is at v il . the power consumption is reduced to the standby level, or to the reset/ power-down level if the power-down function is enabled, independently of the chip enable, output enable or write enable inputs. if reset/power-down is pulled to v ss during a program or erase, this operation is aborted and the memory content is no longer valid. table 5. bus operations operation e g w l rp wait (1) 1. wait signal polarity is configured us ing the set configuration register command. adq15-adq0 bus read v il v il v ih v ih v ih data output bus write v il v ih v il v ih v ih data input address latch v il v ih xv il v ih address input output disable v il v ih v ih v ih v ih hi-z standby v ih x (2) 2. x = don't care. xxv ih hi-z hi-z reset/power- down xxxxv il hi-z hi-z
command interface m58wrxxxku, m58wrxxxkl 22/123 4 command interface all bus write operations to the memory are interpreted by the command interface. commands consist of one or more sequential bus write operations. an internal program/erase controller handles all timings and verifies the correct execution of the program and erase commands. the program/erase controller provides a status register whose output may be read at any time to monitor the progress or the result of the operation. the command interface is reset to read mode when power is first applied, when exiting from reset or whenever v dd is lower than v lko . command sequences must be followed exactly. any invalid combination of commands will be ignored. refer to table 6: command codes , and appendix d , tables 47 , 48 , 49 and 50 , command interface states - modify and lock tables, for a summary of the command interface. the command interface is split into two types of commands: standard commands and factory program commands. the following sections explain in detail how to perform each command. table 6. command codes hex code command 01h block lock confirm 03h set configuration register confirm 10h alternative program setup 20h block erase setup 2fh block lock-down confirm 30h enhanced factory program setup 35h double word program setup 40h program setup 50h clear status register 56h quadruple word program setup 60h block lock setup, block unlock setu p, block lock down setup and set configuration register setup 70h read status register 75h quadruple enhanced factory program setup 90h read electronic signature 98h read cfi query b0h program/erase suspend c0h protection register program d0h program/erase resume, block erase confirm, block unlock confirm or enhanced factory program confirm ffh read array
m58wrxxxku, m58wrxxxkl command interface - standard commands 23/123 5 command interface - standard commands the following commands are the basic commands used to read, write to and configure the device. refer to table 7: standard commands , in conjunction with the following text descriptions. 5.1 read array command the read array command returns the addressed bank to read array mode. one bus write cycle is required to issue the read array command and return the addressed bank to read array mode. subsequent read operations will read the addre ssed location an d output the data. a read array command can be issued in one bank while programming or erasing in another bank. however if a read array command is issued to a bank currently executing a program or erase operation the command will be executed but the output data is not guaranteed. 5.2 read status register command the status register indicates when a program or erase operation is complete and the success or failure of operation itself. issue a read status register command to read the status register content. the read status register command can be issued at any time, even during program or erase operations. the following read operations output the content of the status register of the addressed bank. the status register is la tched on the falling edge of e or g signals, and can be read until e or g returns to v ih . either e or g must be toggled to update the latched data. see ta bl e 1 0 for the description of the status register bits. this mode supports asynchronous or single synchronous reads only. 5.3 read electronic signature command the read electronic signature command reads the manufacturer and device codes, the block locking status, the protection register, and the configuration register. the read electronic signature command consists of one write cycle to an address within one of the banks. a subs equent read operat ion in the same bank will output the manufacturer code, the device code, the protection status of the blocks in the targeted bank, the protection register, or the configuration register (see ta bl e 8 ). the read electronic signature command can be issued at any time, even during program or erase operations, except during protection register program operations. dual operations between the parameter bank and the electronic signature location are not allowed (see table 16: dual operation limitations for details). if a read electronic signature command is issued in a bank that is executing a program or erase operation the bank will go into read electronic sign ature mode, subsequent bus read cycles will output the electronic sig nature data and the prog ram/erase controller will continue to program or erase in the background. this mode supports asynchronous or single synchronous reads only, it does not support synchronous burst reads.
command interface - standard commands m58wrxxxku, m58wrxxxkl 24/123 5.4 read cfi query command the read cfi query command is used to read data from the common flash interface (cfi). the read cfi query command consists of one bus write cycle, to an address within one of the banks. once the command is issued subsequent bus read operations in the same bank read from the common flash interface. if a read cfi query command is issued in a bank that is executing a program or erase operation the bank will go into read cfi quer y mode, subsequent bus read cycles will output the cfi data and the program/erase co ntroller will continue to program or erase in the background. this mode supports asynchro nous or single synchronous reads only, it does not support synchronous burst reads. the status of the other banks is not affected by the command (see ta b l e 1 4 ). after issuing a read cfi query command, a read array command should be issued to the addressed bank to return the bank to read array mode. dual operations between the parameter bank and the cfi memory space are not allowed (see table 16: dual operation limitations ). see appendix b: common flash interface , tables 37 , 38 , 39 , 40 , 41 , 42 , 43 , 44 , 45 and 46 for details on the information contained in the common flash interface memory area. 5.5 clear status register command the clear status register command can be used to reset (set to ?0?) error bits sr1, sr3, sr4 and sr5 in the status register. one bus write cycle is required to issue the clear status register command. after the clear status register command the bank returns to read mode. the error bits in the status register do not automatically return to ?0? when a new command is issued. the error bits in the status register should be cleared before attempting a new program or erase command.
m58wrxxxku, m58wrxxxkl command interface - standard commands 25/123 5.6 block erase command the block erase command can be used to erase a block. it sets all the bits within the selected block to ?1?. all previous data in the block is lost. if the block is protected then the erase operation will abort, the data in the block will not be changed and the status register will output the error. the block erase command can be issued at any moment, regardless of whether the block has been programmed or not. two bus write cycles are required to issue the command. the first bus cycle sets up the erase command. the second latches the block address in the program/erase controller and starts it. if the second bus cycle is not write erase confirm (d0h), status register bits sr4 and sr5 are set and the command aborts. erase aborts if reset turns to v il . as data integrity cannot be guaranteed when the erase operation is aborted, the block must be erased again. once the command is issued the device outputs the status register data when any address within the bank is read. at the end of the op eration the bank will rema in in read status register mode until a read array, read cfi query or read electronic signature command is issued. during erase operations the ba nk containing the block being erased will only accept the read array, read status register, read electronic signature, read cfi query and the program/erase suspend command , all other commands will be ignored. refer to dual operations section for detailed information about simultaneous operations allowed in banks not being erased. typical erase times are given in table 18: program, erase times and endurance cycles . see appendix c , figure 24: block erase flowchart and pseudocode , for a suggested flowchart for using the block erase command. 5.7 program command the memory array can be programmed word-by-word. only one word in one bank can be programmed at any one time. if the block is protected then the program operation will abort, the data in the block will not be changed an d the status register will output the error. two bus write cycles are required to issue the program command. the first bus cycle sets up the program command. the second latches the address and the data to be written and starts the program/erase controller. after programming has started, read operations in the bank being programmed output the status register content. during program operations th e bank being programmed will on ly accept the read array, read status register, read electronic signature, read cfi query and the program/erase suspend command. refer to dual operations section for detailed information about simultaneous operations allowed in banks not being programmed. typical program times are given in table 18: program, erase times and endurance cycles . programming aborts if reset goes to v il . as data integrity cannot be guaranteed when the program operation is aborted, the memory location must be reprogrammed. see appendix c , figure 20: program flowchart and pseudocode , for the flowchart for using the program command.
command interface - standard commands m58wrxxxku, m58wrxxxkl 26/123 5.8 program/erase suspend command the program/erase suspend command is used to pause a program or block erase operation. one bus write cycle is required to issue the program/erase suspend command. once the program/erase controller has paused bits sr7, sr6 and/ or sr2 of th e status register will be set to ?1?. the command can be addressed to any bank. during program/erase suspend the command interface will accept the program/erase resume, read array (cannot read the suspended block), read status register, read electronic signature and read cfi query commands. additionally, if the suspend operation was erase then the clear status register, set configuration register, program, block lock, block lock-down or block unlock command will also be accepted. the block being erased may be protected by issuing the block lock or block lock-down commands. only the blocks not being erased may be read or programmed correctly. when the program/erase resume command is issued the operat ion will complete. refer to the dual operations section for detailed information about simultaneous operations allowed during program/erase suspend. during a program/erase suspend, the device can be placed in standby mode by taking chip enable to v ih . program/erase is aborted if reset turns to v il . see appendix c , figure 23: program suspend & resume flowchart and pseudocode , and figure 25: erase suspend & resume flowchart and pseudocode , for flowcharts for using the program/erase suspend command. 5.9 program/erase resume command the program/erase resume command can be used to restart the program/erase controller after a program/erase suspend command has paused it. one bus write cycle is required to issue the command. the command can be written to any address. the program/erase resume command does not change the read mode of the banks. if the suspended bank was in read status register, read electronic signature or read cfi query mode the bank remains in that mode and outputs the corresponding data. if the bank was in read array mode subsequent read operations will output invalid data. if a program command is issued during a block erase suspend, then the erase cannot be resumed until the programming operation has completed. it is possible to accumulate suspend operations. for example: suspend an erase operation, start a programming operation, suspend the programming operation then read the array. see appendix c , figure 23: program suspend & resume flowchart and pseudocode , and figure 25: erase suspend & resume flowchart and pseudocode , for flowcharts for using the program/erase resume command.
m58wrxxxku, m58wrxxxkl command interface - standard commands 27/123 5.10 protection register program command the protection register program command is used to program the 128 bit user one-time- programmable (otp) segment of the protection register and the protection register lock. the segment is programmed 16 bits at a time. when shipped all bits in the segment are set to ?1?. the user can only program the bits to ?0?. two write cycles are required to issue the protection register program command. the first bus cycle sets up the pr otection register program command. the second latches the address and the data to be written to the protection register and starts the program/erase controller. read operations output the status register content after the programming has started. the segment can be protected by programming bit 1 of the protection lock register ( figure 6: protection register memory map ). attempting to program a previously protected protection register will re sult in a status register error. the protection of the protection register is not reversible. the protection register program cannot be suspended. dual operations between the parameter bank and the protection register memory space are not allowed (see table 16: dual operation limitations for details). see appendix c , figure 27: protection register program flowchart and pseudocode , for a flowchart for using the protection register program command. 5.11 set configuration register command the set configuration register command is used to write a new value to the configuration register which defines the burst length, type , x latency, synchronous/asynchronous read mode and the valid clock edge configuration. two bus write cycles are required to issue the set configuration register command. the first cycle writes the setup command and the address corresponding to the configuration register content. the second cycle writes the configuration register data and the confirm command. once the command is issued the memory returns to read mode. the values of the configuration register must always be presented on adq15-adq0. cr0 is on adq0, cr1 on adq1, etc.; the other address bits are ignored.
command interface - standard commands m58wrxxxku, m58wrxxxkl 28/123 5.12 block lock command the block lock command is used to lock a block and prevent program or erase operations from changing the data in it. all blocks are locked at power-up or reset. two bus write cycles are required to issue the block lock command. the first bus cycle sets up the block lock command. the second bus write cycle latches the block address. the lock status can be monitored for each block using the read electronic signature command. ta b l e 1 7 shows the lock status after issuing a block lock command. the block lock bits are volatile, once set they remain set until a hardware reset or power- down/power-up. they are cleared by a block unlock command. refer to the section, block locking, for a detailed explanation. see appendix c , figure 26: locking operations flowchart and pseudocode , for a flowchart for using the lock command. 5.13 block unlock command the block unlock command is used to unlock a block, allowing the block to be programmed or erased. two bus write cycles are required to issue the block unlock command. the first bus cycle sets up the block unlock command. the second bus write cycle latches the block address. the lock status can be monitored for each block using the read electronic signature command. ta b l e 1 7 shows the protection status after issuing a block unlock command. refer to the section, block locking, for a detailed explanation and appendix c , figure 26: locking operations flowchart and pseudocode , for a flowchart for using the unlock command. 5.14 block lock-down command a locked or unlocked block can be locked-down by issuing the block lock-down command. a locked-down block cannot be programmed or erased, or have its protection status changed when wp is low, v il . when wp is high, v ih, the lock-down function is disabled and the locked blocks can be individually unlocked by the block unlock command. two bus write cycles are required to issue the block lock-down command. the first bus cycle sets up the block lock command. the second bus write cycle latches the block address. the lock status can be monitored for each block using the read electronic signature command. locked-down blocks revert to the locked (and not locked-down) state when the device is reset on power-down. ta bl e 1 7 shows the lock status after issuing a block lock- down command. refer to the section, block locking, for a detailed explanation and appendix c , figure 26: locking operations flowchart and pseudocode , for a flowchart for using the lock-down command.
m58wrxxxku, m58wrxxxkl command interface - standard commands 29/123 table 7. standard commands commands cycles bus operations 1st cycle 2nd cycle op. add data op. add data read array 1+ write bka ffh read wa rd read status register 1+ write bka 70h read bka (1) 1. must be same bank as in the first cyc le. the signature addresses are listed in table 8 srd read electronic signature 1+ write bka 90h read bka (1) esd read cfi query 1+ write bka 98h read bka (1) qd clear status register 1 write x 50h block erase 2 write bka or ba (2) 2. any address within the bank can be used. 20h write ba d0h program 2 write bka or wa (2) 40h or 10h write wa pd program/erase suspend 1 write x (3) 3. x = don't care, wa = word address in targeted ban k, rd = read data, srd = status register data, esd = electronic signature data, qd = query data , ba = block address, bka = bank address, pd = program data, pra = protection register address, prd = protection register data, crd = configuration register data. b0h program/erase resume 1 write x d0h protection register program 2 write pra c0h write pra prd set configuration register 2 write crd 60h write crd 03h block lock 2 write bka or ba (2) 60h write ba 01h block unlock 2 write bka or ba (2) 60h write ba d0h block lock-down 2 write bka or ba (2) 60h write ba 2fh
command interface - standard commands m58wrxxxku, m58wrxxxkl 30/123 figure 6. protection register memory map table 8. electronic signature codes code address (h) data (h) manufacturer code bank address + 00 0020 device code top bank address + 01 8823 (m58wr016ku) 8828 (m58wr032ku) 88c0 (m58wr064ku) bottom bank address + 01 8824 (m58wr016kl) 8829 (m58wr032kl) 88c1 (m58wr064kl) block protection locked block address + 02 0001 unlocked 0000 locked and locked-down 0003 unlocked and locked- down 0002 die revision code bank address + 03 drc (1) 1. drc = die revision code configuration register bank address + 05 cr (2) 2. cr = configuration register protection register lock numonyx factory default bank address + 80 0002 otp area permanently locked 0000 protection register bank address + 81 bank address + 84 unique device number bank address + 85 bank address + 8c otp area ai08614 user programmable otp unique device number protection register lock 1 0 8ch 85h 84h 81h 80h protection register
m58wrxxxku, m58wrxxxkl command interface - factory program commands 31/123 6 command interface - factory program commands the factory program commands are used to speed up programming. they require v pp to be at v pph . refer to table 9: factory program commands , in conjunction with the following text descriptions. 6.1 double word program command the double word program command improves the programming throughput by writing a page of two adjacent words in parallel. the two words must differ only for the address adq0. if the block is protected then the doub le word program operat ion will abort, the data in the block will not be changed and the st atus register will output the error. if programming is attempted with v pp v pph , the command is ignored. three bus write cycles are necessary to issue the double word program command. the first bus cycle sets up the double word program command. the second bus cycle latches the address and the data of the first word to be written. the third bus cycle latches the address and the data of the second word to be written and starts the program/erase controller. read operations in the bank being programmed output the status register content after the programming has started. during double word program operations the bank being programmed will only accept the read array, read status register, read electronic signature and read cfi query command, all other commands w ill be ignored. dual operation s are not supported during double word program operations and the command cannot be suspended. typical program times are given in table 18: program, erase times and endurance cycles . programming aborts if reset goes to v il . as data integrity cannot be guaranteed when the program operation is aborted, the memory locations must be reprogrammed. see appendix c , figure 21: double word program flowchart and pseudocode , for the flowchart for using the double word program command.
command interface - factory program commands m58wrxxxku, m58wrxxxkl 32/123 6.2 quadruple word program command the quadruple word program command improves the programming throughput by writing a page of four adjacent words in parallel. the four words must differ only for the addresses adq0 and adq1. if the block is protected t hen the quadruple word program operation will abort, the data in the block wi ll not be changed and the status register will ou tput the error. if programming is attempted with v pp v pph , the command is ignored. five bus write cycles are necessary to is sue the quadruple word program command. the first bus cycle sets up the double word program command. the second bus cycle latches the address and the data of the first word to be written. the third bus cycle latches the address and the data of the second word to be written. the fourth bus cycle latches the address and the data of the third word to be written. the fifth bus cycle latches the address and the data of the fourth word to be written and starts the program/erase controller. read operations to the bank being programmed output the status register content after the programming has started. programming aborts if reset goes to v il . as data integrity cannot be guaranteed when the program operation is aborted, the memory locations must be reprogrammed. during quadruple word program operations the bank being progra mmed will only accept the read array, read status register, read electronic signature and read cfi query command, all other comma nds will be ignored. dual operations are not supported during quadruple word program operations and the command cannot be suspended. typical program times are given in table 18: program, erase times and endurance cycles . see appendix c , figure 22: quadruple word program flowchart and pseudocode , for the flowchart for using the quadruple word program command.
m58wrxxxku, m58wrxxxkl command interface - factory program commands 33/123 6.3 enhanced factory program command the enhanced factory program command can be used to program large streams of data within any one block. it greatly reduces the total programming time when a large number of words are written to a block at any one time. the use of the enhanced factory program command requires certain operating conditions. v pp must be set to v pph v dd must be within operating range ambient temperature t a must be 30c 10c the targeted block must be unlocked dual operations are not supported during the enhanced factory program operation and the command cannot be suspended. for optimum performance the enhanced factory program commands should be limited to a maximum of 100 program/erase cycles per bloc k. if this limit is exceeded the internal algorithm will continue to work properly but so me degradation in performance is possible. typical program times are given in ta bl e 1 8 . if the block is protected then the enhanced factory program operation will abort, the data in the block will not be changed and the status register will output the error. the enhanced factory program command has four phases: the setup phase, the program phase to program the data to the memory, the verify phase to check that the data has been correctly programmed and reprogram if necessary and the exit phase. refer to ta bl e 9 : factory program commands , and figure 28: enhanced factory program flowchart . 6.3.1 setup phase the enhanced factory program command requires two bus write operations to initiate the command. the first bus cycle sets up the enhanced factory program command. the second bus cycle confirms the command. the status register p/e.c. sr7 should be read to check that the p/e.c. is ready. after the confirm command is issued, read operations output the status register data. the read status register command must not be issued as it will be in terpreted as data to program.
command interface - factory program commands m58wrxxxku, m58wrxxxkl 34/123 6.3.2 program phase the program phase requires n+1 cycles, where n is the number of words (refer to ta bl e 9 : factory program commands and figure 28: enhanced factory program flowchart ). three successive steps are required to issue and execute the program phase of the command. 1. use one bus write operation to latch the start address and the first word to be programmed. the status register bank write status bit sr0 should be read to check that the p/e.c. is ready for the next word. 2. each subsequent word to be programmed is latched with a new bus write operation. the address can either remain the start address, in which case the p/e.c. increments the address location or the address can be incremented in which case the p/e.c. jumps to the new address. if any address that is not in the same block as the start address is given with data ffffh, the program phase terminates and the verify phase begins. the status register bit sr0 should be read between each bus write cycle to check that the p/e.c. is ready for the next word. 3. finally, after all words have been programmed, write one bus write operation with data ffffh to any address outside the block containing the start address, to terminate the programming phase. the memory is now set to enter the verify phase. 6.3.3 verify phase the verify phase is similar to the program phase in that all words must be resent to the memory for them to be checked against the programmed data. the program/erase controller checks the stream of data with the data that was programmed in the program phase and reprograms the memory location if necessary. three successive steps are required to execute the verify phase of the command. 1. use one bus write operation to latch the start address and the first word, to be verified. the status register bit sr0 should be read to check that the program/erase controller is ready for the next word. 2. each subsequent word to be verified is latched with a new bus write operation. the words must be written in the same order as in the program phase. the address can remain the start address or be incremented. if any address that is not in the same block as the start address is given with data ffffh, the verify phase terminates. status register bit sr0 should be read to check that the p/e.c. is ready for the next word. 3. finally, after all words have been verified, write one bus write operation with data ffffh to any address outside the block containing the start address, to terminate the verify phase. if the verify phase is successfully completed the memory remains in read status register mode. if the program/erase controller fails to reprogram a given location, the error will be signaled in the status register. 6.3.4 exit phase status register p/e.c. bit sr7 set to ?1? indicates that the device has returned to read mode. a full status register check should be done to ensure that the block has been successfully programmed. see the section on the status register for more details.
m58wrxxxku, m58wrxxxkl command interface - factory program commands 35/123 6.4 quadruple enhanced factory program command the quadruple enhanced factory program command can be used to program one or more pages of four adjacent words in parallel. the four words must differ only for the addresses adq0 and adq1. v pp must be set to v pph during quadruple enhanced factory program. if the block is protected then the quadruple e nhanced factory progra m operation will abort, the data in the block will not be changed an d the status register will output the error. it has four phases: the setup phase, the load phase where the data is loaded into the buffer, the combined program and verify phase where the loaded data is programmed to the memory and then automatically checked and reprogrammed if necessary and the exit phase. unlike the enhanced factory program it is not necessary to resubmit the data for the verify phase. the load phase and the program and verify phase can be repeated to program any number of pages within the block. 6.4.1 setup phase the quadruple enhanced factory program command requires one bus write operation to initiate the load phase. after the setup command is issued, read operations output the status register data. the read status register command must not be issued as it will be interpreted as data to program. 6.4.2 load phase the load phase requires 4 cycles to load the data (refer to table 9: factory program commands and figure 29: quadruple enhanced factory program flowchart ). once the first word of each page is written it is impossible to exit the load phase until all four words have been written. two successive steps are required to issue an d execute the load phase of the quadruple enhanced factory program command. 1. use one bus write operation to latch the start address and the first word of the first page to be programmed. for subsequent pages the first word address can remain the start address (in which case the next page is programmed) or can be any address in the same block. if any address with data ffffh is given that is not in the same block as the start address, the device enters the exit phase. for the first load phase status register bit sr7 should be read after the fi rst word has been issued to check that the command has been accepted (bit sr7 set to ?0?). this check is not required for subsequent load phases. 2. each subsequent word to be programmed is latched with a new bus write operation. the address is only checked for the first word of each page as the order of the words to be programmed is fixed. the memory is now set to enter the program and verify phase.
command interface - factory program commands m58wrxxxku, m58wrxxxkl 36/123 6.4.3 program and verify phase in the program and verify phase the four words that were loaded in the load phase are programmed in the memory array and then verified by the program/erase controller. if any errors are found the program/erase controller reprograms the location. during this phase the status register shows that the program/erase controller is busy, status register bit sr7 set to ?0?, and that the device is not waiting for new data, status register bit sr0 set to ?1?. when status register bit sr0 is set to ?0? the program and verify phase has terminated. once the verify phase has successfully completed subsequent pages in the same block can be loaded and programmed. the device returns to the beginning of the load phase by issuing one bus write operation to latch the address and the first of the four new words to be programmed. 6.4.4 exit phase finally, after all the pages have been programmed, write one bus write operation with data ffffh to any address outside the block containing the start address, to terminate the load and program and verify phases. status register bit sr7 set to ?1? and bit sr0 set to ?0? indicate that the quadruple enhanced factory program command has terminated. a full status register check should be done to ensure that the block has been successfully programmed. see the section on the status register for more details. if the program and verify phase has successfully completed the memory returns to read mode. if the p/e.c. fails to program and re program a given locati on, the error will be signaled in the status register.
m58wrxxxku, m58wrxxxkl command interface - factory program commands 37/123 table 9. factory program commands (1) command phase cycles bus write operations 1st 2nd 3rd final -1 final add data add data add data add data add data double word program (2) 3 bka or wa1 (3) 35h wa1 pd1 wa2 pd2 quadruple word program (4) 5 bka or wa1 (3) 56h wa1 pd1 wa2 pd2 wa3 pd3 wa4 pd4 enhanced factory program (5) setup, program 2+n +1 bka or wa1 (3) 30h ba or wa1 (6) d0h wa1 (7) pd1 wan (8) pa n not wa1 (7)) ffff h verify, exit n+1 wa1 (7) pd1 wa2 (8) pd2 wa3 (8) pd3 wan (8) pa n not wa1 (7) ffff h quadruple enhanced factory program (4)(5) setup, first load 5 bka or wa1 (3) 75h wa1 (7) pd1 wa2 (9) pd2 wa3 (9) pd3 wa4 (9) pd4 first program & ver ify automatic subsequent loads 4wa1i (7) pd1i wa2i (9) pd2i wa3i (9) pd3i wa4i (9) pd4i subsequent program & ver ify automatic exit 1 not wa1 (7) ffffh 1. wa = word address in targeted bank, bka = bank address, pd = program da ta, ba = block address. 2. word addresses 1 and 2 must be consecutive addresses differing only for a0. 3. any address within the bank can be used. 4. word addresses 1,2,3 and 4 must be consecut ive addresses differing only for a0 and a1. 5. a bus read must be done between each write cycle where the dat a is programmed or verified to read the status register and check that the memory is ready to accept the next data. n = number of words, i = number of pages to be programmed. 6. any address within the block can be used. 7. wa1 is the start address. not wa1 is any add ress that is not in the same block as wa1. 8. address can remain starting address wa1 or be incremented. 9. address is only checked for the first word of each page as the order to program the words in each page is fixed so subsequent words in each page c an be written to any address.
status register m58wrxxxku, m58wrxxxkl 38/123 7 status register the status register provides information on the current or previous program or erase operations. issue a read status register command to read the contents of the status register, refer to read status register command section for more details. to output the contents, the status register is latched and up dated on the falling edge of the chip enable or output enable signals and can be read until chip enable or output enable returns to v ih . the status register can only be read using single asynchronous or single synchronous reads. bus read operations from any address within the bank, always read the status register during program and erase operations. the various bits convey information about the status and any errors of the operation. bits sr7, sr6, sr2 and sr0 give information on the status of the device and are set and reset by the device. bits sr5, sr4, sr3 and sr1 give information on errors, they are set by the device but must be reset by issuing a clear status register command or a hardware reset. if an error bit is set to ?1? the status register should be reset before issuing another command. sr7 to sr1 refer to the status of the device while sr0 refers to the status of the addressed bank. the bits in the status register are summarized in table 10: status register bits . refer to ta bl e 1 0 in conjunction with the following text descriptions. 7.1 program/erase controller status bit (sr7) the program/erase controller status bit indicates whether the program/erase controller is active or inactive in any bank. when the program/erase controller status bit is low (set to ?0?), the program/erase controller is active ; when the bit is high (set to ?1?), the program/erase controller is inactive, and the device is ready to process a new command. the program/erase controller status is low immediately after a program/erase suspend command is issued until the program/erase controller pauses. after the program/erase controller pauses the bit is high. during program, erase, operations the program/erase controller status bit can be polled to find the end of the operation. other bits in the status register should not be tested until the program/erase controller completes the operation and the bit is high. after the program/erase controller completes its operation the erase status, program status, v pp status and block lock status bits should be tested for errors. 7.2 erase suspend status bit (sr6) the erase suspend status bit indicates that an erase operation has been suspended or is going to be suspended in the addressed block. when the erase suspend status bit is high (set to ?1?), a program/erase suspend command has been issued and the memory is waiting for a program/erase resume command. the erase suspend status should only be considered valid when the program/erase controller status bit is high (program/erase c ontroller inactive). sr7 is set within the erase suspend latency time of the program/erase suspend command being issued therefore the memory may still complete th e operation rather than entering the suspend mode. when a program/erase resume command is issued the erase suspend status bit returns low.
m58wrxxxku, m58wrxxxkl status register 39/123 7.3 erase status bit (sr5) the erase status bit can be used to identify if the memory has failed to verify that the block has erased correctly. when the erase status bit is high (set to ?1?), the program/erase controller has applied th e maximum number of pulses to the block and still failed to verify that it has erased correctly. the erase status bit should be read once the program/erase controller status bit is high (p rogram/erase controller inactive). once set high, the erase status bit can only be reset low by a clear status register command or a hardware reset. if set high it should be reset before a new program or erase command is issued, otherwise t he new command will appear to fail. 7.4 program status bit (sr4) the program status bit is used to identify either a program failure, or an attempt to program a ?1? to an already programmed bit when v pp = v pph . when the program status bit goes high (set to ?1?) after a program failure, the program/erase controller has applied the maximu m number of pulses to the byte and still failed to verify that it has programmed correctly. after an attempt to program a ?1? to an already programmed bit, the program status bit sr4 only goes high (set to ?1?) if v pp = v pph (if v pp v pph , sr4 remains low (set to ?0?) and the attempt is not shown). the program status bit should be read once the program/erase controller status bit is high (program/erase controller inactive). once set high, the program status bit can only be reset low by a clear status register command or a hardware reset. if set high it should be reset before a new command is issued, otherwise the new command will appear to fail. 7.5 v pp status bit (sr3) the v pp status bit can be used to identify an invalid voltage on the v pp pin during program and erase operations. the v pp pin is only sampled at the beginning of a program or erase operation. indeterminate results can occur if v pp becomes invalid during an operation. when the v pp status bit is low (set to ?0?), the voltage on the v pp pin was sampled at a valid voltage; when the v pp status bit is high (set to ?1?), the v pp pin has a voltage that is below the v pp lockout voltage, v pplk , the memory is protected and program and erase operations cannot be performed. once set high, the v pp status bit can only be reset low by a clear status register command or a hardware reset. if set high it should be reset before a new program or erase command is issued, otherwise t he new command will appear to fail.
status register m58wrxxxku, m58wrxxxkl 40/123 7.6 program suspend status bit (sr2) the program suspend status bit indicates that a program operation has been suspended in the addressed block. when the program suspend status bit is high (set to ?1?), a program/erase suspend command has been issued and the memory is waiting for a program/erase resume command. the program suspend status should only be considered valid when the program/erase controller status bit is high (program/erase controller inactive). sr2 is set within the program suspend latency time of the program/erase suspend command being issued therefore t he memory may still complete the operation rather than entering the suspend mode. when a program/erase resume command is issued the program suspend status bit returns low. 7.7 block protection status bit (sr1) the block protection status bit can be used to identify if a program or block erase operation has tried to modify the contents of a locked block. when the block protection status bit is high (set to ?1?), a program or erase operation has been attempted on a locked block. once set high, the block protection status bit can only be reset low by a clear status register command or a hardware reset. if set high it should be reset before a new command is issued, otherwise t he new command will appear to fail. 7.8 bank write/multiple word program status bit (sr0) the bank write status bit indicates whether t he addressed bank is programming or erasing. in enhanced factory program mode the multiple word program bit shows if a word has finished programming or verifying depending on the phase. the bank write status bit should only be considered valid when the program/erase controller status sr7 is low (set to ?0?). when both the program/erase controller status bit and the bank write status bit are low (set to ?0?), the addressed bank is executing a program or erase operation. when the program/erase controller status bit is low (set to ?0?) and the bank write status bit is high (set to ?1?), a program or erase operation is being executed in a bank other than the one being addressed. in enhanced factory program mode if multiple word program status bit is low (set to ?0?), the device is ready for the next word, if the multiple word program status bit is high (set to ?1?) the device is not ready for the next word. note: refer to appendix c: flowcharts and pseudocodes , for using the status register.
m58wrxxxku, m58wrxxxkl status register 41/123 table 10. status register bits bit name type logic level (1) definition sr7 p/e.c. status status '1' ready '0' busy sr6 erase suspend status status '1' erase suspended '0' erase in progress or completed sr5 erase status error '1' erase error '0' erase success sr4 program status error '1' program error '0' program success sr3 v pp status error '1' v pp invalid, abort '0' v pp ok sr2 program suspend status status '1' program suspended '0' program in progress or completed sr1 block protection status error '1' program/erase on protected block, abort '0' no operation to protected blocks sr0 bank write status status '1' sr7 = ?1? not allowed sr7 = ?0? program or erase operation in a bank other than the addressed bank '0' sr7 = ?1? no program or erase operation in the device sr7 = ?0? program or erase operation in addressed bank multiple word program status (enhanced factory program mode) status '1' sr7 = ?1? not allowed sr7 = ?0? the device is not ready for the next word '0' sr7 = ?1? the device is exiting from efp sr7 = ?0? the device is ready for the next word 1. logic level '1' is high, '0' is low.
configuration register m58wrxxxku, m58wrxxxkl 42/123 8 configuration register the configuration register is used to configur e the type of bus access that the memory will perform. refer to read modes section for details on read operations. the configuration register is set through the command interface. after a reset or power- up the device is configured for asynchronous read (cr15 = 1). the configuration register bits are described in ta bl e 1 2 they specify the selection of the burst length, burst type, burst x latency and the read operation. refer to figures 7 and 8 for examples of synchronous burst configurations. 8.1 read select bit (cr15) the read select bit, cr15, is used to switch between asynchronous and synchronous bus read operations. when the read select bit is set to ?1?, read operations are asynchronous; when the read select bit is set to ?0?, read operations are synchronous. synchronous burst read is supported in both parameter and main blocks and can be performed across banks. on reset or power-up the read select bit is set to?1? for asynchronous access. 8.2 bus invert configuration (cr14) the bus invert configuration bit is used to enable the binv functionality. when the functionality is enabled, if the binv pin operates as an input pin (during write bus operations), the binv signal must always be dr iven; if it operates as an output pin (during read bus operations), the functionality is valid only during synchronous read operations.
m58wrxxxku, m58wrxxxkl configuration register 43/123 8.3 x-latency bits (cr13-cr11) the x-latency bits are used during synchronous read operations to set the number of clock cycles between the address being latched and the first data becoming available. refer to figure 7: x-latency and data output configuration example . for correct operation the x-latency bits can only assume the values in ta b l e 1 2 : configuration register . ta bl e 1 1 shows how to set the x-latency parameter, taking into account the speed class of the device and the frequency used to read the flash memory in synchronous mode. 8.4 wait polarity bit (cr10) in synchronous burst mode the wait signal indicates whether the output data are valid or a wait state must be inserted. the wait polarity bit is used to set the polarity of the wait signal. when the wait polarity bit is set to ?0? the wait signal is active low. when the wait polarity bit is set to ?1? the wait signal is active high. 8.5 data output configuration bit (cr9) the data output configuration bit determines whether the output remains valid for one or two clock cycles. when the data output configur ation bit is ?0? the output data is valid for one clock cycle, when the data output configurat ion bit is ?1? the output data is valid for two clock cycles. the data output configuration depends on the condition: t k > t kqv + t qvk_cpu where t k is the clock period, t qvk_cpu is the data setup time required by the system cpu and t kqv is the clock to data valid time. if this condition is not satisfied, the data output configuration bit should be set to ?1? (two clock cycles). refer to figure 7: x-latency and data output configuration example . 8.6 wait configuration bit (cr8) in burst mode the wait bit controls the timing of the wait output pin, wait. when wait is asserted, data is not valid and when wait is deasserted, data is valid. when the wait bit is ?0? the wait output pin is asserted during the wait state. when the wait bit is ?1? the wait output pin is asserted one clock cycle before the wait state. table 11. x-latency settings fmax t k min x-latency min 30 mhz 33 ns 2 40 mhz 25 ns 3 54 mhz 19 ns 4 66 mhz 15 ns 4 86 mhz 12 ns 5
configuration register m58wrxxxku, m58wrxxxkl 44/123 8.7 burst type bit (cr7) the burst type bit is used to configure the sequence of addresses read as sequential or interleaved. when the burst type bit is ?0? the memory outputs from interleaved addresses; when the burst type bit is ?1? the memory outputs from sequential addresses. see ta bl e 1 3 : burst type definition , for the sequence of addresses output from a given starting address in each mode. 8.8 valid clock edge bit (cr6) the valid clock edge bit, cr6, is used to configure the active edge of the clock, k, during synchronous burst read operatio ns. when the valid clock edge bit is ?0? the falling edge of the clock is the active edge; when the valid clock edge bit is ?1? the rising edge of the clock is active. 8.9 power-down bit (cr5) the power-down bit is used to enable or disable the power-down function. when it is set to ?0? the power-down function is disabled. if the reset/power-down, rp , pin goes low (v il ), the device is reset an d the supply current i dd is reduced to the standby value i dd3 . when the power-down bit is set to ?1? the power-down function is enabled. if the reset/power- down, rp , pin goes low (v il ) the device switches to the power-down state and the supply current i dd is reduced to the reset/power-down value, i dd2 . the recovery time after a reset/power-down, rp , pulse is significantly longer when power- down is enabled (see table 28: reset and power-up ac characteristics ). 8.10 wrap burst bit (cr3) the burst reads can be confined inside the 4, 8 or 16 word boundary (wrap) or overcome the boundary (no wrap). the wrap burst bit is used to select between wrap and no wrap. when the wrap burst bit is set to ?0? the burst read wraps; when it is set to ?1? the burst read does not wrap.
m58wrxxxku, m58wrxxxkl configuration register 45/123 8.11 burst length bits (cr2-cr0) the burst length bits set the number of words to be output during a synchronous burst read operation as result of a single address latch cycle. they can be set for 4 words, 8 words, 16 words or continuous burst, where all the words are read sequentially. in continuous burst mode the burst sequence can cross bank boundaries. in continuous burst mode or in 4, 8, 16 words no-wrap, depending on the starting address, the device asserts the wait output to indicate that a delay is necessary before the data is output. if the starting address is aligned to a 4 word boundary no wait states are needed and the wait output is not asserted. if the starting address is shifted by 1, 2 or 3 positions from the four word boundary, wait will be asserted for 1, 2 or 3 clock cycles when the burst sequence crosses the first 16 word boundary, to indicate that the device needs an internal delay to read the successive words in the array. wait will be asserted only once during a continuous burst access. see also table 13: burst type definition . cr4 is reserved for future use.
configuration register m58wrxxxku, m58wrxxxkl 46/123 table 12. configuration register bit description value description cr15 read select 0 synchronous read 1 asynchronous read (default at power-on) cr14 bus invert configuration 0 binv (power save) disabled (default) 1 binv (power save) enabled cr13-cr11 x-latency 010 2 clock latency 011 3 clock latency 100 4 clock latency 101 5 clock latency 111 reserved (default) other configurations reserved cr10 wait polarity 0 wait is active low (default) 1 wait is active high cr9 data output configuration 0 data held for one clock cycle 1 data held for two clock cycles (default) cr8 wait configuration 0 wait is active during wait state (default) 1 wait is active one data cycle before wait state cr7 burst type 0 interleaved 1 sequential (default) cr6 valid clock edge 0 falling clock edge 1 rising clock edge (default) cr5 power-down configuration 0 power-down disabled (default) 1 power-down enabled cr4 reserved cr3 wrap burst 0wrap 1 no wrap (default) cr2-cr0 burst length 001 4 words 010 8 words 011 16 words 111 continuous (cr7 must be set to ?1?) (default)
m58wrxxxku, m58wrxxxkl configuration register 47/123 table 13. burst type definition mode start add 4 words 8 words 16 words continuous burst sequen- tial inter- leaved sequential interleaved sequential interleaved wrap 0 0-1-2-3 0-1-2-3 0-1-2-3-4- 5-6-7 0-1-2-3-4-5- 6-7 0-1-2-3-4-5-6-7-8- 9-10-11-12-13-14- 15 0-1-2-3-4-5-6- 7-8-9-10-11- 12-13-14-15 0-1-2-3-4-5-6... 1 1-2-3-0 1-0-3-2 1-2-3-4-5- 6-7-0 1-0-3-2-5-4- 7-6 1-2-3-4-5-6-7-8-9- 10-11-12-13-14- 15-0 1-0-3-2-5-4-7- 6-9-8-11-10- 13-12-15-14 1-2-3-4-5-6-7- ...15-wait-16- 17-18... 2 2-3-0-1 2-3-0-1 2-3-4-5-6- 7-0-1 2-3-0-1-6-7- 4-5 2-3-4-5-6-7-8-9- 10-11-12-13-14- 15-0-1 2-3-0-1-6-7-4- 5-10-11-8-9- 14-15-12-13 2-3-4-5-6-7...15- wait-wait-16- 17-18... 3 3-0-1-2 3-2-1-0 3-4-5-6-7- 0-1-2 3-2-1-0-7-6- 5-4 3-4-5-6-7-8-9-10- 11-12-13-14-15-0- 1-2 3-2-1-0-7-6-5- 4-11-10-9-8- 15-14-13-12 3-4-5-6-7...15- wait-wait- wait-16-17- 18... ... 7 7-4-5-6 7-6-5-4 7-0-1-2-3- 4-5-6 7-6-5-4-3-2- 1-0 7-8-9-10-11-12-13- 14-15-0-1-2-3-4-5- 6 7-6-5-4-3-2-1- 0-15-14-13- 12-11-10-9-8 7-8-9-10-11-12- 13-14-15-wait- wait-wait-16- 17... ... 12 12-13-14-15-16- 17-18... 13 13-14-15-wait- 16-17-18... 14 14-15-wait- wait-16-17- 18.... 15 15-wait-wait- wait-16-17- 18...
configuration register m58wrxxxku, m58wrxxxkl 48/123 no-wrap 0 0-1-2-3 0-1-2-3-4- 5-6-7 0-1-2-3-4-5-6-7-8- 9-10-11-12-13-14- 15 same as for wrap (wrap /no wrap has no effect on continuous burst) 1 1-2-3-4 1-2-3-4-5- 6-7-8 1-2-3-4-5-6-7-8-9- 10-11-12-13-14- 15-wait-16 2 2-3-4-5 2-3-4-5-6- 7-8-9... 2-3-4-5-6-7-8-9- 10-11-12-13-14- 15-wait-wait-16- 17 3 3-4-5-6 3-4-5-6-7- 8-9-10 3-4-5-6-7-8-9-10- 11-12-13-14-15- wait-wait-wait- 16-17-18 ... 7 7-8-9-10 7-8-9-10- 11-12-13- 14 7-8-9-10-11-12-13- 14-15-wait-wait- wait-16-17-18-19- 20-21-22 ... 12 12-13-14- 15 12-13-14- 15-16-17- 18-19 12-13-14-15-16- 17-18-19-20-21- 22-23-24-25-26-27 13 13-14-15- wait-16 13-14-15- wait-16- 17-18-19- 20 13-14-15-wait-16- 17-18-19-20-21- 22-23-24-25-26- 27-28 14 14-15- wait- wait-16- 17 14-15- wait- wait-16- 17-18-19- 20-21 14-15-wait-wait- 16-17-18-19-20- 21-22-23-24-25- 26-27-28-29 15 15-wait- wait- wait-16- 17-18 15-wait- wait- wait-16- 17-18-19- 20-21-22 15-wait-wait- wait-16-17-18-19- 20-21-22-23-24- 25-26-27-28-29-30 table 13. burst type definition (continued) mode start add 4 words 8 words 16 words continuous burst sequen- tial inter- leaved sequential interleaved sequential interleaved
m58wrxxxku, m58wrxxxkl configuration register 49/123 figure 7. x-latency and data output configuration example 1. amax is equal to a19 in the m58wr016ku/l, to a20 in the m58wr032ku/l, and to a21 in the m58wr064ku/l. 2. settings shown: x-latency = 4, data output held for one clock cycle. ai13522 a16-amax (1) valid address k l adq15-adq0 valid data x-latency valid data tk tqvk_cpu tkqv 1st cycle 2nd cycle 3rd cycle 4th cycle e valid address
configuration register m58wrxxxku, m58wrxxxkl 50/123 figure 8. wait configuration example 1. amax is equal to a19 in the m58wr016ku/l, to a20 in the m58wr032ku/l, and to a21 in the m58wr064ku/l. ai13523 a16-amax (1) valid address k l adq15-adq0 valid address valid data wait cr8 = '0' cr10 = '0' wait cr8 = '1' cr10 = '0' valid data not valid valid data e wait cr8 = '0' cr10 = '1' wait cr8 = '1' cr10 = '1' g
m58wrxxxku, m58wrxxxkl read modes 51/123 9 read modes read operations can be performed in two different ways depending on the settings in the configuration register. if the clock signal is ?don?t care? for the data output, the read operation is asynchronous; if the data output is synchronized with clock, the read operation is synchronous. the read mode and data output format are determined by the configuration register. (see configuration register section for details). all banks supports both asynchronous and synchronous read operations. the multiple bank architecture allows read operations in one bank, while write operations are bei ng executed in another (see tables 14 and 15 ). 9.1 asynchronous read mode in asynchronous read operations the clock signal is ?don?t care?. the device outputs the data corresponding to the address latched, th at is the memory array, status register, common flash interface or electronic signat ure depending on the command issued. cr15 in the configuration register must be set to ?1? for asynchronous operations. in asynchronous read mode, the wait signal is always deasserted. the device features an automatic standby mode. during asynchronous read operations, after a bus inactivity of 150 ns, the device au tomatically switches to the automatic standby mode. in this condition the power consumption is reduced to the standby value i dd4 and the outputs are still driven. see table 24: asynchronous read ac characteristics , and figure 11: asynchronous random access read ac waveforms .
read modes m58wrxxxku, m58wrxxxkl 52/123 9.2 synchronous burst read mode in synchronous burst read mode the data is output in bursts synchronized with the clock. it is possible to perform burst reads across bank boundaries. synchronous burst read mode can only be used to read the memory array. for other read operations, such as read status register, read cfi and read electronic signature, single synchronous read or asynchronous random access read must be used. in synchronous burst read mode the flow of the data output depends on parameters that are configured in the configuration register. a burst sequence is started at the first clock edge (rising or falling depending on valid clock edge bit cr6 in the configuration registe r) after the falling edge of latch enable. addresses are internally incremented and after a delay of 2 to 5 clock cycles (x latency bits cr13-cr11) the corresponding data are output on each clock cycle. the number of words to be output during a synchronous burst read operation can be configured as 4, 8 or 16 words or continuous (burst length bits cr2-cr0). the data can be configured to remain valid for one or two clock cycles (data output configuration bit cr9). the order of the data output can be modified through the burst type and the wrap burst bits in the configuration register. the burst sequence may be configured to be sequential or interleaved (cr7). the burst reads can be confined inside the 4, 8 or 16 word boundary (wrap) or overcome the boundary (no wrap). if the starting address is aligned to the burst length (4, 8 or 16 words), the wrapped configuration has no impact on the output sequence. interleaved mode is not allowed in continuous burst read mode or with no wrap sequences. a wait signal may be asserted to indicate to the system that an output delay will occur. this delay will depend on the starting address of the burst sequence; the worst case delay will occur when the sequence is crossing a 16 word boundary and the starting address was at the end of a four word boundary. wait is asserted during x-latency, the wait state and at the end of a 4, 8 and 16 word burst. it is only deasserted when output data are valid or when g is at v ih . in continuous burst read mode a wait state will oc cur when crossing the first 16 word boundary. if the burst starting address is aligned to a 4 wo rd page, the wait state will not occur. the wait signal can be configured to be active low or active high by setting cr10 in the configuration register. see table 25: synchronous read ac characteristics , and figure 12: synchronous burst read ac waveforms , for details.
m58wrxxxku, m58wrxxxkl read modes 53/123 9.2.1 synchronous burst read suspend a synchronous burst read operation can be suspended, freeing the data bus for other higher priority devices. it can be suspended during the initial access latency time (before data is output) or after the device has output data. when the synchronous burst read operation is suspended, internal array sensing continues and any previously latched internal data is retained. a burst sequence can be su spended and resumed as often as required as long as the operating conditions of the device are met. a synchronous burst read operation is suspended when e is low and the current address has been latched (on a latch enable rising edge or on a valid clock edge). the clock signal is then halted at v ih or at v il , and g goes high. when g becomes low again and the clock signal restarts, the synchronous burst read operation is resumed exactly where it stopped. wait being gated by e remains active and will not re vert to high-im pedance when g goes high. so if two or more devices are connecte d to the system?s ready signal, to prevent bus contention the wait signal of the flash memo ry should not be directly connected to the system?s ready signal. see table 25: synchronous read ac characteristics , and figure 14: synchronous burst read suspend ac waveforms for details. 9.3 single synchronous read mode single synchronous read operations are sim ilar to synchronous burst read operations except that only the first data output after the x latency is valid. synchronous single reads are used to read the electronic signature, status register, cfi, block protection status, configuration register status or protection register. when the addressed bank is in read cfi, read status register or read electronic signature mode, the wait signal is deasserted when output enable, g , is at v ih or for the one clock cycle during which output data is va lid. otherwise, it is asserted. see table 25: synchronous read ac characteristics and figure 13: single synchronous read ac waveforms , for details.
dual operations and multiple bank architecture m58wrxxxku, m58wrxxxkl 54/123 10 dual operations and multiple bank architecture the multiple bank architectu re of the m58wrxxxku/l prov ides flexibility for software developers by allowing code and data to be split with 4 mbit granularity. the dual operations feature simplifies the software management of the device and allows code to be executed from one bank while another bank is being programmed or erased. the dual operations feature means that while programming or erasing in one bank, read operations are possible in another bank with zero latency (only one bank at a time is allowed to be in program or erase mode). if a read operation is required in a bank which is programming or erasing, the program or erase operation can be suspended. also if the suspended operation was erase then a program command can be issued to another block, so the device can have one block in erase suspend mode, one programming and other banks in read mode. bus read operations are allowed in another bank between setup and confirm cycles of program or erase operations. the combination of these features means that read operations are possible at any moment. dual operations between the parameter bank and either of the cfi, the otp or the electronic signature memory space are not allowed. ta bl e 1 6 shows which dual operations are allowed or not between the cfi, the otp, the electronic signature locations and the memory array. ta bl e s 14 and 15 show the dual operations possible in other banks and in the same bank. note that only the commonly used commands are represented in these tables. for a complete list of possib le commands refer to appendix d: command interface state tables . table 14. dual operations allowed in other banks status of bank commands allowed in another bank read array read status register read cfi query read electronic signature program erase program/ erase suspend program/ erase resume i d l e ye s ye s ye s ye s ye s ye s ye s ye s programming yes yes yes yes ? ? yes ? erasing yes yes yes yes ? ? yes ? program suspended ye s ye s ye s ye s ? ? ? ye s erase suspended ye s ye s ye s ye s ye s ? ? ye s
m58wrxxxku, m58wrxxxkl dual operations and multiple bank architecture 55/123 table 15. dual operations allowed in same bank status of bank commands allowed in same bank read array read status register read cfi query read electronic signature program erase program/ erase suspend program/ erase resume i d l e ye s ye s ye s ye s ye s ye s ye s ye s programming ? (1)) 1. the read array command is accepted but the data output is not guaranteed until the program or erase has completed. ye s ye s ye s ? ? ye s ? erasing ? (1) ye s ye s ye s ? ? ye s ? program suspended ye s (2) 2. not allowed in the block or word that is being erased or programmed. ye s ye s ye s ? ? ? ye s erase suspended ye s (2) ye s ye s ye s ye s (2) ?? yes table 16. dual operation limitations current status commands allowed read cfi / otp / electronic signature read parameter blocks read main blocks located in parameter bank not located in parameter bank programming / erasing parameter blocks no no no yes programming / erasing main blocks located in parameter bank ye s n o n o ye s not located in parameter bank ye s ye s ye s in different bank only programming otp no no no no
block locking m58wrxxxku, m58wrxxxkl 56/123 11 block locking the m58wrxxxku/l features an in stant, individual block locking scheme that allows any block to be locked or unlocked with no latency. this locking scheme has three levels of protection. lock/unlock - this first level allows software-only control of block locking. lock-down - this second level requires hardware interaction before locking can be changed. v pp v pplk - the third level offers a complete hardware protection against program and erase on all blocks. the protection status of each block can be set to locked, unlocked, and lock-down. ta bl e 1 7 , defines all of the possible protection states (wp , dq1, dq0), and appendix c: flowcharts and pseudocodes , figure 26 , shows a flowchart for the locking operations. 11.1 reading a block?s lock status the lock status of every block can be read in the read electronic signature mode of the device. to enter this mode write 90h to the device. subsequent reads at the address specified in ta bl e 8 , will output the protection status of that block. the lock status is represented by dq0 and dq1. dq0 indicates the block lock/unlock status and is set by the lock command and cleared by the unlock command. it is also automatically set when entering lock-down. dq1 indicates the lock-down status and is set by the lock-down command. it cannot be cleared by software, only by a hardware reset or power-down. the following sections explain the operation of the locking system. 11.2 locked state the default status of all blocks on power-up or after a hardware reset is locked (states (0,0,1) or (1,0,1)). locked blocks are fully protected from any program or erase. any program or erase operations attempted on a lo cked block will return an error in the status register. the status of a locked block can be changed to unlocked or lock-down using the appropriate software commands. an unlocked block can be locked by issuing the lock command. 11.3 unlocked state unlocked blocks (states (0,0,0), (1,0,0) (1,1,0)), can be programmed or erased. all unlocked blocks return to the locked state after a hardware reset or when the device is powered- down. the status of an unlocked block can be changed to locked or locked-down using the appropriate software commands. a locked block can be unlocked by issuing the unlock command.
m58wrxxxku, m58wrxxxkl block locking 57/123 11.4 lock-down state blocks that are locked-down (state (0,1,x))are protected from program and erase operations (as for locked blocks) but their protection status cannot be changed using software commands alone. a locked or unlocked block can be locked-down by issuing the lock-down command. locked-down blocks revert to the locked state when the device is reset or powered-down. the lock-down function is dependent on the wp input pin. when wp =0 (v il ), the blocks in the lock-down state (0,1,x) are protected from program, erase and protection status changes. when wp =1 (v ih ) the lock-down function is disabled (1,1,x) and locked-down blocks can be individually unlocked to the (1,1,0) state by issuing the software command, where they can be erased and programmed. these blocks can then be re-locked (1,1,1) and unlocked (1,1,0) as desired while wp remains high. when wp is low, blocks that were previously locked-down return to the lock-down state (0,1,x) regardless of any changes made while wp was high. device reset or power-down resets all blocks, including those in lock-down, to the locked state. 11.5 locking operations during erase suspend changes to block lock status can be performed during an erase suspend by using the standard locking command sequences to unlock, lock or lock-down a block. this is useful in the case when another block needs to be updated while an erase operation is in progress. to change block locking during an erase operation, first write the erase suspend command, then check the status register until it indicates that the erase operation has been suspended. next write the desired lock command sequence to a block and the lock status will be changed. after completing any desired lock, read, or pr ogram operations, resume the erase operation with the erase resume command. if a block is locked or locked-down during an erase suspend of the same block, the locking status bits will be changed immediately, but when the erase is resumed, the erase operation will complete. locking operations cannot be per formed during a program suspend. refer to appendix d: command interface state tables , for detailed informatio n on which commands are valid during erase suspend.
block locking m58wrxxxku, m58wrxxxkl 58/123 table 17. lock status current protection status (1) (wp , adq1, adq0) 1. the lock status is defined by the write protect pin and by dq1 (?1? for a locked-down block) and dq0 (?1? for a locked block) as read in the read elec tronic signature command with a1 = v ih and a0 = v il . next protection status (1) (wp , adq1, adq0) current state program/erase allowed after block lock command after block unlock command after block lock-down command after wp transition 1,0,0 yes 1,0,1 1,0,0 1,1,1 0,0,0 1,0,1 (2) 2. all blocks are locked at power-up, so the de fault configuration is 001 or 101 according to wp status. no 1,0,1 1,0,0 1,1,1 0,0,1 1,1,0 yes 1,1,1 1,1,0 1,1,1 0,1,1 1,1,1 no 1,1,1 1,1,0 1,1,1 0,1,1 0,0,0 yes 0,0,1 0,0,0 0,1,1 1,0,0 0,0,1 (2) no 0,0,1 0,0,0 0,1,1 1,0,1 0,1,1 no 0,1,1 0,1,1 0,1 ,1 1,1,1 or 1,1,0 (3) 3. a wp transition to v ih on a locked block will restore the pr evious dq0 value, giving a 111 or 110.
m58wrxxxku, m58wrxxxkl program and erase times and endurance cycles 59/123 12 program and erase times and endurance cycles the program and erase times and the number of program/ erase cycles per block are shown in ta b l e 1 8 in the m58wrxxxku/l the maximum number of program/ erase cycles depends on the voltage supply used. table 18. program, erase times and endurance cycles (1) parameter condition min typ typical after 100k w/e cycles max unit v pp = v dd erase parameter block (4 kword) (2) 0.3 1 2.5 s main block (32 kword) preprogrammed 0.8 3 4 s not preprogrammed 1 4 s program (3) word 12 12 100 s parameter block (4 kword) 40 ms main block (32 kword) 300 ms suspend latency program 5 10 s erase 5 20 s program/erase cycles (per block) main blocks 100,000 cycles parameter blocks 100,000 cycles v pp = v pph erase parameter block (4 kword) 0.25 2.5 s main block (32 kword) 0.8 4 s program (3) word/ double word/ quadruple word (4) 10 100 s parameter block (4 kword) quad-enhanced factory 11 ms enhanced factory 45 ms quadruple word (4) 10 ms word 40 ms main block (32 kword) quad-enhanced factory 94 ms enhanced factory 360 ms quadruple word (4) 80 ms word 328 ms bank (4mbit) quad-enhanced factory (4) 0.75 s quadruple word (4) 0.65 s program/erase cycles (per block) main blocks 1000 cycles parameter blocks 2500 cycles 1. t a = ?40 to 85c; v dd = v ddq = 1.7 v to 2 v. 2. the difference between preprogrammed and not preprogrammed is not significant (?30 ms). 3. values are liable to change with the external system- level overhead (command sequence and status register polling execution). 4. measurements performed at 25c. t a = 30c 10c for quadruple word, double word and quadruple enhanced factory program.
maximum rating m58wrxxxku, m58wrxxxkl 60/123 13 maximum rating stressing the device above the rating listed in the absolute maximum ratings table may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliabilit y. refer also to the numonyx sure program and other relevant quality documents. table 19. absolute maximum ratings symbol parameter value unit min max t a ambient operating temperature ?40 85 c t bias temperature under bias ?40 125 c t stg storage temperature ?65 155 c v io input or output voltage ?0.5 v ddq +0.6 v v dd supply voltage ?0.2 2.45 v v ddq input/output supply voltage ?0.2 2.45 v v pp program voltage ?0.2 10.0 v i o output short circuit current 100 ma t vpph time for v pp at v pph 100 hours
m58wrxxxku, m58wrxxxkl dc and ac parameters 61/123 14 dc and ac parameters this section summarizes the operating measurement conditions, and the dc and ac characteristics of the device. the parameters in the dc and ac characteristics tables that follow, are derived from tests performed under the measurement conditions summarized in table 20: operating and ac measurement conditions . designers should check that the operating conditions in their circuit match the operating conditions when relying on the quoted parameters. figure 9. ac measurement i/o waveform table 20. operating and ac measurement conditions parameter m58wrxxxku/l unit 60 ns 70 ns min max min max v dd supply voltage 1.7 2 1.7 2 v v ddq supply voltage 1.7 2 1.7 2 v v pp supply voltage (factory environment) 8.5 9.5 8.5 9.5 v v pp supply voltage (application environment) ?0.4 v ddq +0.4 ?0.4 v ddq +0.4 v ambient operating temperature ?40 85 ?40 85 c load capacitance (c l )3030pf input rise and fall times 5 5 ns input pulse voltages 0 to v ddq 0 to v ddq v input and output timing ref. voltages v ddq /2 v ddq /2 v ai06161 v ddq 0v v ddq /2
dc and ac parameters m58wrxxxku, m58wrxxxkl 62/123 figure 10. ac measurement load circuit table 21. capacitance (1) 1. sampled only, not 100% tested. symbol parameter test condition min max unit c in input capacitance v in = 0 v 6 8 pf c out output capacitance v out = 0 v 8 12 pf ai06162 v ddq c l c l includes jig capacitance 16.7k device under test 0.1f v dd 0.1f v ddq 16.7k
m58wrxxxku, m58wrxxxkl dc and ac parameters 63/123 table 22. dc characteristics - currents symbol parameter test condition min typ max unit i li input leakage current 0v v in v ddq 1 a i lo output leakage current 0v v out v ddq 1 a i dd1 supply current asynchronous read (f=6 mhz) e = v il , g = v ih 10 20 ma supply current synchronous read (f=66 mhz) 4 word 18 20 ma 8 word 20 22 ma 16 word 22 24 ma continuous 24 26 ma supply current synchronous read (f=86 mhz) 4 word 22 25 ma 8 word 25 27 ma 16 word 30 32 ma continuous 33 35 ma i dd2 supply current (reset/power-down) rp = v ss 0.2 v 2 10 a i dd3 supply current (standby) e = v ddq 0.2 v, k = v ss 15 50 a i dd4 supply current (automatic standby) e = v il , g = v ih 15 50 a i dd5 (1) 1. sampled only, not 100% tested. supply current (program) v pp = v pph 10 30 ma v pp = v dd 20 34 ma supply current (erase) v pp = v pph 10 30 ma v pp = v dd 20 34 ma i dd6 (1)(2) 2. v dd dual operation current is the sum of read and program or erase currents. supply current (dual operations) program/erase in one bank, asynchronous read in another bank 30 54 ma program/erase in one bank, synchronous read (continuous burst 66 mhz) in another bank 44 60 ma i dd7 (1) supply current program/ erase suspended (standby) e = v ddq 0.2 v, k = v ss 15 50 a i pp1 (1) v pp supply current (program) v pp = v pph 510ma v pp = v dd 0.2 5 a v pp supply current (erase) v pp = v pph 510ma v pp = v dd 0.2 5 a i pp2 v pp supply current (read) v pp = v pph 100 400 a v pp v dd 0.2 5 a i pp3 (1) v pp supply current (standby) v pp v dd 0.2 5 a
dc and ac parameters m58wrxxxku, m58wrxxxkl 64/123 table 23. dc characteristics - voltages symbol parameter test condition min typ max unit v il input low voltage ?0.5 0.4 v v ih input high voltage v ddq ?0.4 v ddq + 0.4 v v ol output low voltage i ol = 100 a 0.1 v v oh output high voltage i oh = ?100 a v ddq ?0.1 v v pp1 v pp program voltage-logic program, erase 1.3 2.4 v v pph v pp program voltage factory program, erase 8.5 9 9.5 v v pplk program or erase lockout 0.4 v v lko v dd lock voltage 1 v
m58wrxxxku, m58wrxxxkl dc and ac parameters 65/123 figure 11. asynchronous random access read ac waveforms ai13524 tavav tehqx tglqv tglqx tghqx e g telqv tehqz tghqz adq0-adq15 valid address valid l tellh tllqv tlllh tavlh tlhax wait (2) teltv tehtz notes: 1- wait is active low. 2- amax is equal to a19 in the m58wr016ku/l, to a20 in the m58wr032ku/l, and to a21 in the m58wr064ku/l. valid address latch outputs enabled data valid standby tlhgl hi-z valid address tavqv hi-z a16-amax (1) valid data
dc and ac parameters m58wrxxxku, m58wrxxxkl 66/123 table 24. asynchronous read ac characteristics symbol alt parameter m58wrxxxku/l unit 60 70 read timings t avav t rc address valid to next address valid min 60 70 ns t avqv t acc address valid to output valid (random) max 60 70 ns t eltv chip enable low to wait valid max 9 11 ns t elqv (1) 1. g may be delayed by up to t elqv - t glqv after the falling edge of e without increasing t elqv . t ce chip enable low to output valid max 60 70 ns t ehtz chip enable high to wait hi-z max 11 14 ns t ehqx (2) 2. sampled only, not 100% tested. t oh chip enable high to output transition min 0 0 ns t ehqz (2) t hz chip enable high to output hi-z max 11 14 ns t glqv (1) t oe output enable low to output valid max 20 20 ns t glqx (2) t olz output enable low to output tr a n s i t i o n min 0 0 ns t ghqx (2) t oh output enable high to output tr a n s i t i o n min 0 0 ns t ghqz (2) t df output enable high to output hi-z max 11 14 ns latch timings t avlh t avadvh address valid to latch enable high min 4 7 ns t ellh t eladvh chip enable low to latch enable high min 9 10 ns t lhax t advhax latch enable high to address tr a n s i t i o n min 4 7 ns t lllh t advladvh latch enable pulse width min 7 7 ns t llqv t advlqv latch enable low to output valid (random) max 60 70 ns t lhgl t advhgl latch enable high to output enable low min 4 5 ns
m58wrxxxku, m58wrxxxkl dc and ac parameters 67/123 figure 12. synchronous burst read ac waveforms ai13525 adq0-adq15 e g a16-amax (5) l wait k valid valid valid address tlllh tavlh tglqx tavkh tllkh telkh tkhax tkhqx tkhqv not valid valid note 1 note 2 note 2 tkhtx tehqx tehqz tghqx tghqz hi-z valid note 2 teltv tkhtv tehtz address latch x latency valid data flow boundary crossing valid data standby note 1. the number of clock cycles to be inserted depends on the x latency set in the configuration register. 2. the wait signal can be configured to be active during wait state or one cycle before. wait signal is active low. 3. address latched and data output on the rising clock edge. tehel valid address valid not valid valid valid binv (4) 4. the binv signal has the waveform shown only if it has been enabled with the configuration register. if it is disabled, it re mains low. 5. amax is equal to a19 in the m58wr016ku/l, to a20 in the m58wr032ku/l, and to a21 in the m58wr064ku/l. tgltv tglqv
dc and ac parameters m58wrxxxku, m58wrxxxkl 68/123 figure 13. single synchronous read ac waveforms ai13526 adq0-adq15 e g a16-amax (5) l wait (2) k (3) valid not valid valid address tlllh tavlh tglqv tavkh tllkh telkh tkhax not valid not valid note 1 tehqx tehqz tghqx tghqz hi-z not valid teltv tkhqv tehtz note 1. the number of clock cycles to be inserted depends on the x latency set in the configuration register. 2. the wait signal is configured to be active during wait state. wait signal is active low. 3. address latched and data output on the rising clock edge. not valid tglqx tehel tkhtv 4. the binv signal has the shown waveform only if it has been enabled with the configuration register. when disabled, it remain s low. 5. amax is equal to a19 in the m58wr016ku/l, to a20 in the m58wr032ku/l, and to a21 in the m58wr064ku/l. valid address not valid not valid not valid not valid not valid binv (4) tgltv tghtv
m58wrxxxku, m58wrxxxkl dc and ac parameters 69/123 figure 14. synchronous burst read suspend ac waveforms ai13527 adq0-adq15 e g a16-amax (6) l wait (2) k (4) valid valid valid address tlllh tavlh tglqv tavkh tllkh telkh tkhax valid valid note 1 tehqx tehqz tghqx hi-z teltv tkhqv tehtz note 1. the number of clock cycles to be inserted depends on the x latency set in the configuration register. 2. the wait signal is configured to be active during wait state. wait signal is active low. 3. the clock signal can be held high or low 4. address latched and data output on the rising clock edge. tglqx tehel 5. the binv signal has the shown waveform only if it has been enabled with the configuration register. when disabled, it remain s low. 6. amax is equal to a19 in the m58wr016ku/l, to a20 in the m58wr032ku/l, and to a21 in the m58wr064ku/l. valid address valid valid valid binv (5) tghqz note 3 tgltv
dc and ac parameters m58wrxxxku, m58wrxxxkl 70/123 figure 15. clock input ac waveform 1. sampled only, not 100% tested. for other timings please refer to table 24: asynchronous read ac characteristics . table 25. synchronous read ac characteristics symbol alt parameter m58wrxxxku/l unit 60 70 synchronous read timings t avkh t avclkh address valid to clock high min 4 5 ns t elkh t elclkh chip enable low to clock high min 4 5 ns t eltv chip enable low to wait valid max 9 11 ns t ehel chip enable pulse width (subsequent synchronous reads) min 11 14 ns t ehtz chip enable high to wait hi-z max 11 14 ns t ghtv output enable high to wait valid min 11 11 ns t gltv output enable low to wait valid max 11 11 ns t khax t clkhax clock high to address transition min 6 7 ns t khqv t khtv t clkhqv clock high to output valid clock high to wait valid max 9 11 ns t khqx t khtx t clkhqx clock high to output transition clock high to wait transition min 2 3 ns t llkh t advlclkh latch enable low to clock high min 4 5 ns clock specifications t khkh t clk clock period (66 mhz) min 15 ns clock period (f=86 mhz) 12 t khkl t klkh clock high to clock low clock low to clock high min 3.5 3.5 ns t f t r clock fall or rise time max 3 3 ns ai06981 tkhkh tf tr tkhkl tklkh
m58wrxxxku, m58wrxxxkl dc and ac parameters 71/123 figure 16. write ac waveforms, write enable controlled ai13528 adq0-adq15 l g bank addr. a16-amax (1) e tlllh w bank address wp v pp tavav valid valid valid command valid addr. status register binv valid addr. cmd or data valid address valid address tlhax tavlh tellh tghll tlhgl telqv twlwh telwl twheh twhdx tdvwh twhwl twhel tvphwh twphwh twhwpl tqvwpl twhvpl tqvvpl twhkv status register read 1 st polling twhll confirm command set-up command k program or erase note 1: amax is equal to a19 in the m58wr016ku/l, to a20 in the m58wr032ku/l, and to a21 in the m58wr064ku/l.
dc and ac parameters m58wrxxxku, m58wrxxxkl 72/123 2. sampled only, not 100% tested. table 26. write ac characteristics, write enable controlled symbol alt parameter m58wrxxxku/l unit 60 70 write enable controlled timings t avav t wc address valid to next address valid min 60 70 ns t avlh address valid to latch enable high min 4 7 ns t dvwh t ds data valid to write enable high min 40 40 ns t ellh chip enable low to latch enable high min 9 10 ns t elwl t cs chip enable low to write enable low min 0 0 ns t elqv chip enable low to output valid min 60 70 ns t ghll output enable high to latch enable low min 14 20 ns t ghwl output enable high to write enable low min 14 20 ns t lhax latch enable high to address transition min 4 7 ns t lhgl latch enable high to output enable low min 4 5 ns t lllh latch enable pulse width min 7 7 ns t whdx t dh write enable high to input transition min 0 0 ns t wheh t ch write enable high to chip enable high min 0 0 ns t whel (1) 1. t whel and t whll have this value when reading from the targ eted bank or when reading from any address after a set configuration register command has been issued. system designers should take this into account and may insert a software no-op instruction to delay the first read in t he same bank after issuing any command, or to delay the first read to any addr ess after issuing a set configuration register command. if the first read after the command is a r ead array operation in a different bank and no changes to the configuration register have been issued, t whel and t whll are 0 ns. write enable high to chip enable low min 25 25 ns t whgl write enable high to output enable low min 0 0 ns t whll (1) write enable high to latch enable low min 25 25 ns t whwl t wph write enable high to write enable low min 25 25 ns t wlwh t wp write enable low to write enable high min 40 45 ns protection timings t qvvpl output (status register) valid to v pp low min 0 0 ns t qvwpl output (status register) valid to write protect low min 0 0 ns t vphwh t vps v pp high to write enable high min 200 200 ns t whvpl write enable high to v pp low min 200 200 ns t whwpl write enable high to write protect low min 200 200 ns t wphwh write protect high to write enable high min 200 200 ns
m58wrxxxku, m58wrxxxkl dc and ac parameters 73/123 figure 17. write ac waveforms, chip enable controlled ai13529 adq0-adq15 l g bank addr. a16-amax (1) e tlllh w bank address wp v pp tavav valid valid valid command valid addr. status register binv valid addr. cmd or data valid address valid address tlhax tavlh tellh tghll tlhgl telqv teleh tehel tehdx tdveh twhel tvpheh twpheh tehwpl tqvwpl tehvpl tqvvpl twhkv status register read 1 st polling tehll confirm command set-up command k program or erase twlel tehwh note 1: amax is equal to a19 in the m58wr016ku/l, to a20 in the m58wr032ku/l, and to a21 in the m58wr064ku/l.
dc and ac parameters m58wrxxxku, m58wrxxxkl 74/123 1. sampled only, not 100% tested. 2. t whel has this value when reading from the targeted ban k or when reading from any address after a set configuration register command has been issued. system designers shoul d take this into account and may insert a software no-op instruction to delay the first read in the same bank after issuing any command, or to delay the first read to any address after issuing a set configuration register command. if the first read after the command is a read array operation in a different bank and no changes to the configuration regist er have been issued, t whel is 0 ns. table 27. write ac characteristics, chip enable controlled symbol alt parameter m58wrxxxku/l unit 60 70 chip enable controlled timings t avav t wc address valid to next address valid min 60 70 ns t avlh address valid to latch enable high min 4 7 ns t dveh t ds data valid to chip enable high min 40 40 ns t ehdx t dh chip enable high to input transition min 0 0 ns t ehel t wph chip enable high to chip enable low min 25 25 ns t ehll chip enable high to latch enable low min 0 0 ns t ehwh t ch chip enable high to write enable high min 0 0 ns t eleh t wp chip enable low to chip enable high min 40 45 ns t ellh chip enable low to latch enable high min 9 10 ns t elqv chip enable low to output valid min 60 70 ns t ghel output enable high to chip enable low min 14 20 ns t ghll output enable high to latch enable low min 14 20 ns t lhax latch enable high to address transition min 4 7 ns t lhgl latch enable high to output enable low min 4 5 ns t lllh latch enable pulse width min 7 7 ns t whel (2) write enable high to chip enable low min 25 25 ns t wlel t cs write enable low to chip enable low min 0 0 ns protection timings t ehvpl chip enable high to v pp low min 200 200 ns t ehwpl chip enable high to write protect low min 200 200 ns t qvvpl output (status register) valid to v pp low min 0 0 ns t qvwpl output (status register) valid to write protect low min 0 0 ns t vpheh t vps v pp high to chip enable high min 200 200 ns t wpheh write protect high to chip enable high min 200 200 ns
m58wrxxxku, m58wrxxxkl dc and ac parameters 75/123 figure 18. reset and power-up ac waveforms ai06976 w, rp e, g, vdd, vddq tvdhph tplph power-up reset tplwl tplel tplgl tplll l tphwl tphel tphgl tphll table 28. reset and power-up ac characteristics symbol parameter test condition 60 70 unit t plwl t plel t plgl t plll reset low to write enable low, chip enable low, output enable low, latch enable low during program min 10 10 s during erase min 20 20 s after power-down min 50 50 s other conditions min 80 80 ns t phwl t phel t phgl t phll reset high to write enable low chip enable low output enable low latch enable low min 30 30 ns t plph (1)(2) rp pulse width min 50 50 ns t vdhph (3) supply voltages high to reset high min 200 200 s 1. the device reset is possible but not guaranteed if t plph < 50 ns. 2. sampled only, not 100% tested. 3. it is important to assert rp in order to allow proper cpu initialization during power-up or reset.
package mechanical m58wrxxxku, m58wrxxxkl 76/123 15 package mechanical in order to meet environmental requirements, numonyx offers these devices in ecopack? packages. these packages have a lead-free second-level interconnect. the category of second-level interconnect is marked on the package and on the inner box label, in compliance with jedec standard jesd97. the maximum ratings related to soldering conditions are also marked on the inner box label. figure 19. vfbga44 7.5 5 mm, 10 4 ball array, 0.50 mm pitch, bottom view package outline 1. drawing is not to scale. a2 a1 bga-z52 d d1 fd b e e1 ddd sd se fe a ball "a1" e2 d2 fd1 fe1 e
m58wrxxxku, m58wrxxxkl package mechanical 77/123 table 29. vfbga44 7.5 5 mm, 10 4 ball array, 0.50 mm pitch, package mechanical data symbol millimeters inches typ min max typ min max a 1.000 0.0394 a1 0.150 0.0059 a2 0.660 0.0260 b 0.300 0.250 0.350 0.0118 0.0098 0.0138 d 7.500 7.400 7.600 0.2953 0.2913 0.2992 d1 4.500 0.1772 d2 6.500 0.2559 ddd 0.080 0.0031 e 5.000 4.900 5.100 0.1969 0.1929 0.2008 e1 1.500 0.0591 e2 3.500 0.1378 e 0.500 ? ? 0.0197 ? ? fd 1.500 0.0591 fd1 0.500 0.0197 fe 1.750 0.0689 fe1 0.750 0.0295 sd 0.250 0.0098 se 0.250 0.0098
part numbering m58wrxxxku, m58wrxxxkl 78/123 16 part numbering devices are shipped from the factory with the memory content bits erased to ?1?. for a list of available options (speed, package, etc.), daisy chain ordering information, or for further information on any aspect of this device, please contact the numonyx sales office nearest to you. table 30. ordering information scheme example: m58 w r 032 k u 70 za 6 e device type m58 architecture w = multiple bank, burst mode operating voltage r = v dd = v ddq = 1.7v to 2v density 016 = 16 mbit ( 16) 032 = 32 mbit ( 16) 064 = 64 mbit ( 16) technology k = 65 nm technology parameter location u = top boot, mux i/o l = bottom boot, mux i/o speed 60 = 60 ns 70 = 70 ns package za = vfbga44 7.5 x 5 mm, 0.50 mm pitch temperature range 6 = ?40 to 85 c option e = ecopack? package, standard packing u = ecopack? package, tape & reel packing, 16mm
m58wrxxxku, m58wrxxxkl block address tables 79/123 appendix a block address tables table 31. top boot block addresses, m58wr016ku bank (1) # size (kword) address range parameter bank 0 4 ff000-fffff 1 4 fe000-fefff 2 4 fd000-fdfff 3 4 fc000-fcfff 4 4 fb000-fbfff 5 4 fa000-fafff 6 4 f9000-f9fff 7 4 f8000-f8fff 8 32 f0000-f7fff 9 32 e8000-effff 10 32 e0000-e7fff 11 32 d8000-dffff 12 32 d0000-d7fff 13 32 c8000-cffff 14 32 c0000-c7fff bank 1 15 32 b8000-bffff 16 32 b0000-b7fff 17 32 a8000-affff 18 32 a0000-a7fff 19 32 98000-9ffff 20 32 90000-97fff 21 32 88000-8ffff 22 32 80000-87fff bank 2 23 32 78000-7ffff 24 32 70000-77fff 25 32 68000-6ffff 26 32 60000-67fff 27 32 58000-5ffff 28 32 50000-57fff 29 32 48000-4ffff 30 32 40000-47fff
block address tables m58wrxxxku, m58wrxxxkl 80/123 bank 3 31 32 38000-3ffff 32 32 30000-37fff 33 32 28000-2ffff 34 32 20000-27fff 35 32 18000-1ffff 36 32 10000-17fff 37 32 08000-0ffff 38 32 00000-07fff 1. there are two bank regions: bank region 1 contains all the banks that are made up of main blocks only; bank region 2 contains the banks that are made up of the parameter and main blocks (parameter bank). table 32. bottom boot block addresses, m58wr016kl bank (1) # size (kword) address range bank 3 38 32 f8000-fffff 37 32 f0000-f7fff 36 32 e8000-effff 35 32 e0000-e7fff 34 32 d8000-dffff 33 32 d0000-d7fff 32 32 c8000-cffff 31 32 c0000-c7fff bank 2 30 32 b8000-bffff 29 32 b0000-b7fff 28 32 a8000-affff 27 32 a0000-a7fff 26 32 98000-9ffff 25 32 90000-97fff 24 32 88000-8ffff 23 32 80000-87fff table 31. top boot block addresses, m58wr016ku (continued) bank (1) # size (kword) address range
m58wrxxxku, m58wrxxxkl block address tables 81/123 bank 1 22 32 78000-7ffff 21 32 70000-77fff 20 32 68000-6ffff 19 32 60000-67fff 18 32 58000-5ffff 17 32 50000-57fff 16 32 48000-4ffff 15 32 40000-47fff parameter bank 14 32 38000-3ffff 13 32 30000-37fff 12 32 28000-2ffff 11 32 20000-27fff 10 32 18000-1ffff 9 32 10000-17fff 8 32 08000-0ffff 7 4 07000-07fff 6 4 06000-06fff 5 4 05000-05fff 4 4 04000-04fff 3 4 03000-03fff 2 4 02000-02fff 1 4 01000-01fff 0 4 00000-00fff 1. there are two bank regions: bank region 2 contains all the banks that are made up of main blocks only; bank region 1 contains the banks that are made up of the parameter and main blocks (parameter bank). table 32. bottom boot block addresses, m58wr016kl (continued) bank (1) # size (kword) address range
block address tables m58wrxxxku, m58wrxxxkl 82/123 table 33. top boot block addresses, m58wr032ku bank (1) # size (kword) address range parameter bank 0 4 1ff000-1fffff 1 4 1fe000-1fefff 2 4 1fd000-1fdfff 3 4 1fc000-1fcfff 4 4 1fb000-1fbfff 5 4 1fa000-1fafff 6 4 1f9000-1f9fff 7 4 1f8000-1f8fff 8 32 1f0000-1f7fff 9 32 1e8000-1effff 10 32 1e0000-1e7fff 11 32 1d8000-1dffff 12 32 1d0000-1d7fff 13 32 1c8000-1cffff 14 32 1c0000-1c7fff bank 1 15 32 1b8000-1bffff 16 32 1b0000-1b7fff 17 32 1a8000-1affff 18 32 1a0000-1a7fff 19 32 198000-19ffff 20 32 190000-197fff 21 32 188000-18ffff 22 32 180000-187fff bank 2 23 32 178000-17ffff 24 32 170000-177fff 25 32 168000-16ffff 26 32 160000-167fff 27 32 158000-15ffff 28 32 150000-157fff 29 32 148000-14ffff 30 32 140000-147fff bank 3 31 32 138000-13ffff 32 32 130000-137fff 33 32 128000-12ffff 34 32 120000-127fff 35 32 118000-11ffff 36 32 110000-117fff 37 32 108000-10ffff 38 32 100000-107fff
m58wrxxxku, m58wrxxxkl block address tables 83/123 bank 4 39 32 0f8000-0fffff 40 32 0f0000-0f7fff 41 32 0e8000-0effff 42 32 0e0000-0e7fff 43 32 0d8000-0dffff 44 32 0d0000-0d7fff 45 32 0c8000-0cffff 46 32 0c0000-0c7fff bank 5 47 32 0b8000-0bffff 48 32 0b0000-0b7fff 49 32 0a8000-0affff 50 32 0a0000-0a7fff 51 32 098000-09ffff 52 32 090000-097fff 53 32 088000-08ffff 54 32 080000-087fff bank 6 55 32 078000-07ffff 56 32 070000-077fff 57 32 068000-06ffff 58 32 060000-067fff 59 32 058000-05ffff 60 32 050000-057fff 61 32 048000-04ffff 62 32 040000-047fff bank 7 63 32 038000-03ffff 64 32 030000-037fff 65 32 028000-02ffff 66 32 020000-027fff 67 32 018000-01ffff 68 32 010000-017fff 69 32 008000-00ffff 70 32 000000-007fff 1. there are two bank regions: bank region 1 contains all the banks that are made up of main blocks only; bank region 2 contains the banks that are made up of the parameter and main blocks (parameter bank). table 33. top boot block addresses, m58wr032ku (continued) bank (1) # size (kword) address range
block address tables m58wrxxxku, m58wrxxxkl 84/123 table 34. bottom boot block addresses, m58wr032kl bank (1) # size (kword) address range bank 7 70 32 1f8000-1fffff 69 32 1f0000-1f7fff 68 32 1e8000-1effff 67 32 1e0000-1e7fff 66 32 1d8000-1dffff 65 32 1d0000-1d7fff 64 32 1c8000-1cffff 63 32 1c0000-1c7fff bank 6 62 32 1b8000-1bffff 61 32 1b0000-1b7fff 60 32 1a8000-1affff 59 32 1a0000-1a7fff 58 32 198000-19ffff 57 32 190000-197fff 56 32 188000-18ffff 55 32 180000-187fff bank 5 54 32 178000-17ffff 53 32 170000-177fff 52 32 168000-16ffff 51 32 160000-167fff 50 32 158000-15ffff 49 32 150000-157fff 48 32 148000-14ffff 47 32 140000-147fff bank 4 46 32 138000-13ffff 45 32 130000-137fff 44 32 128000-12ffff 43 32 120000-127fff 42 32 118000-11ffff 41 32 110000-117fff 40 32 108000-10ffff 39 32 100000-107fff
m58wrxxxku, m58wrxxxkl block address tables 85/123 bank 3 38 32 0f8000-0fffff 37 32 0f0000-0f7fff 36 32 0e8000-0effff 35 32 0e0000-0e7fff 34 32 0d8000-0dffff 33 32 0d0000-0d7fff 32 32 0c8000-0cffff 31 32 0c0000-0c7fff bank 2 30 32 0b8000-0bffff 29 32 0b0000-0b7fff 28 32 0a8000-0affff 27 32 0a0000-0a7fff 26 32 098000-09ffff 25 32 090000-097fff 24 32 088000-08ffff 23 32 080000-087fff bank 1 22 32 078000-07ffff 21 32 070000-077fff 20 32 068000-06ffff 19 32 060000-067fff 18 32 058000-05ffff 17 32 050000-057fff 16 32 048000-04ffff 15 32 040000-047fff table 34. bottom boot block addresses, m58wr032kl (continued) bank (1) # size (kword) address range
block address tables m58wrxxxku, m58wrxxxkl 86/123 parameter bank 14 32 038000-03ffff 13 32 030000-037fff 12 32 028000-02ffff 11 32 020000-027fff 10 32 018000-01ffff 9 32 010000-017fff 8 32 008000-00ffff 7 4 007000-007fff 6 4 006000-006fff 5 4 005000-005fff 4 4 004000-004fff 3 4 003000-003fff 2 4 002000-002fff 1 4 001000-001fff 0 4 000000-000fff 1. there are two bank regions: bank region 2 contains all the banks that are made up of main blocks only; bank region 1 contains the banks that are made up of the parameter and main blocks (parameter bank). table 34. bottom boot block addresses, m58wr032kl (continued) bank (1) # size (kword) address range
m58wrxxxku, m58wrxxxkl block address tables 87/123 table 35. top boot block addresses, m58wr064ku bank (1) # size (kword) address range parameter bank 0 4 3ff000-3fffff 1 4 3fe000-3fefff 2 4 3fd000-3fdfff 3 4 3fc000-3fcfff 4 4 3fb000-3fbfff 5 4 3fa000-3fafff 6 4 3f9000-3f9fff 7 4 3f8000-3f8fff 8 32 3f0000-3f7fff 9 32 3e8000-3effff 10 32 3e0000-3e7fff 11 32 3d8000-3dffff 12 32 3d0000-3d7fff 13 32 3c8000-3cffff 14 32 3c0000-3c7fff bank 1 15 32 3b8000-3bffff 16 32 3b0000-3b7fff 17 32 3a8000-3affff 18 32 3a0000-3a7fff 19 32 398000-39ffff 20 32 390000-397fff 21 32 388000-38ffff 22 32 380000-387fff bank 2 23 32 378000-37ffff 24 32 370000-377fff 25 32 368000-36ffff 26 32 360000-367fff 27 32 358000-35ffff 28 32 350000-357fff 29 32 348000-34ffff 30 32 340000-347fff bank 3 31 32 338000-33ffff 32 32 330000-337fff 33 32 328000-32ffff 34 32 320000-327fff 35 32 318000-31ffff 36 32 310000-317fff 37 32 308000-30ffff 38 32 300000-307fff
block address tables m58wrxxxku, m58wrxxxkl 88/123 bank 4 39 32 2f8000-2fffff 40 32 2f0000-2f7fff 41 32 2e8000-2effff 42 32 2e0000-2e7fff 43 32 2d8000-2dffff 44 32 2d0000-2d7fff 45 32 2c8000-2cffff 46 32 2c0000-2c7fff bank 5 47 32 2b8000-2bffff 48 32 2b0000-2b7fff 49 32 2a8000-2affff 50 32 2a0000-2a7fff 51 32 298000-29ffff 52 32 290000-297fff 53 32 288000-28ffff 54 32 280000-287fff bank 6 55 32 278000-27ffff 56 32 270000-277fff 57 32 268000-26ffff 58 32 260000-267fff 59 32 258000-25ffff 60 32 250000-257fff 61 32 248000-24ffff 62 32 240000-247fff bank 7 63 32 238000-23ffff 64 32 230000-237fff 65 32 228000-22ffff 66 32 220000-227fff 67 32 218000-21ffff 68 32 210000-217fff 69 32 208000-20ffff 70 32 200000-207fff bank 8 71 32 1f8000-1fffff 72 32 1f0000-1f7fff 73 32 1e8000-1effff 74 32 1e0000-1e7fff 75 32 1d8000-1dffff 76 32 1d0000-1d7fff 77 32 1c8000-1cffff 78 32 1c0000-1c7fff table 35. top boot block addresses, m58wr064ku (continued) bank (1) # size (kword) address range
m58wrxxxku, m58wrxxxkl block address tables 89/123 bank 9 79 32 1b8000-1bffff 80 32 1b0000-1b7fff 81 32 1a8000-1affff 82 32 1a0000-1a7fff 83 32 198000-19ffff 84 32 190000-197fff 85 32 188000-18ffff 86 32 180000-187fff bank 10 87 32 178000-17ffff 88 32 170000-177fff 89 32 168000-16ffff 90 32 160000-167fff 91 32 158000-15ffff 92 32 150000-157fff 93 32 148000-14ffff 94 32 140000-147fff bank 11 95 32 138000-13ffff 96 32 130000-137fff 97 32 128000-12ffff 98 32 120000-127fff 99 32 118000-11ffff 100 32 110000-117fff 101 32 108000-10ffff 102 32 100000-107fff bank 12 103 32 0f8000-0fffff 104 32 0f0000-0f7fff 105 32 0e8000-0effff 106 32 0e0000-0e7fff 107 32 0d8000-0dffff 108 32 0d0000-0d7fff 109 32 0c8000-0cffff 110 32 0c0000-0c7fff bank 13 111 32 0b8000-0bffff 112 32 0b0000-0b7fff 113 32 0a8000-0affff 114 32 0a0000-0a7fff 115 32 098000-09ffff 116 32 090000-097fff 117 32 088000-08ffff 118 32 080000-087fff table 35. top boot block addresses, m58wr064ku (continued) bank (1) # size (kword) address range
block address tables m58wrxxxku, m58wrxxxkl 90/123 bank 14 119 32 078000-07ffff 120 32 070000-077fff 121 32 068000-06ffff 122 32 060000-067fff 123 32 058000-05ffff 124 32 050000-057fff 125 32 048000-04ffff 126 32 040000-047fff bank 15 127 32 038000-03ffff 128 32 030000-037fff 129 32 028000-02ffff 130 32 020000-027fff 131 32 018000-01ffff 132 32 010000-017fff 133 32 008000-00ffff 134 32 000000-007fff 1. there are two bank regions: bank region 1 contains all the banks that are made up of main blocks only; bank region 2 contains the banks that are made up of the parameter and main blocks (parameter bank). table 36. bottom boot block addresses, m58wr064kl bank (1) # size (kword) address range bank 15 134 32 3f8000-3fffff 133 32 3f0000-3f7fff 132 32 3e8000-3effff 131 32 3e0000-3e7fff 130 32 3d8000-3dffff 129 32 3d0000-3d7fff 128 32 3c8000-3cffff 127 32 3c0000-3c7fff bank 14 126 32 3b8000-3bffff 125 32 3b0000-3b7fff 124 32 3a8000-3affff 123 32 3a0000-3a7fff 122 32 398000-39ffff 121 32 390000-397fff 120 32 388000-38ffff 119 32 380000-387fff table 35. top boot block addresses, m58wr064ku (continued) bank (1) # size (kword) address range
m58wrxxxku, m58wrxxxkl block address tables 91/123 bank 13 118 32 378000-37ffff 117 32 370000-377fff 116 32 368000-36ffff 115 32 360000-367fff 114 32 358000-35ffff 113 32 350000-357fff 112 32 348000-34ffff 111 32 340000-347fff bank 12 110 32 338000-33ffff 109 32 330000-337fff 108 32 328000-32ffff 107 32 320000-327fff 106 32 318000-31ffff 105 32 310000-317fff 104 32 308000-30ffff 103 32 300000-307fff bank 11 102 32 2f8000-2fffff 101 32 2f0000-2f7fff 100 32 2e8000-2effff 99 32 2e0000-2e7fff 98 32 2d8000-2dffff 97 32 2d0000-2d7fff 96 32 2c8000-2cffff 95 32 2c0000-2c7fff bank 10 94 32 2b8000-2bffff 93 32 2b0000-2b7fff 92 32 2a8000-2affff 91 32 2a0000-2a7fff 90 32 298000-29ffff 89 32 290000-297fff 88 32 288000-28ffff 87 32 280000-287fff table 36. bottom boot block addresses, m58wr064kl (continued) bank (1) # size (kword) address range
block address tables m58wrxxxku, m58wrxxxkl 92/123 bank 9 86 32 278000-27ffff 85 32 270000-277fff 84 32 268000-26ffff 83 32 260000-267fff 82 32 258000-25ffff 81 32 250000-257fff 80 32 248000-24ffff 79 32 240000-247fff bank 8 78 32 238000-23ffff 77 32 230000-237fff 76 32 228000-22ffff 75 32 220000-227fff 74 32 218000-21ffff 73 32 210000-217fff 72 32 208000-20ffff 71 32 200000-207fff bank 7 70 32 1f8000-1fffff 69 32 1f0000-1f7fff 68 32 1e8000-1effff 67 32 1e0000-1e7fff 66 32 1d8000-1dffff 65 32 1d0000-1d7fff 64 32 1c8000-1cffff 63 32 1c0000-1c7fff bank 6 62 32 1b8000-1bffff 61 32 1b0000-1b7fff 60 32 1a8000-1affff 59 32 1a0000-1a7fff 58 32 198000-19ffff 57 32 190000-197fff 56 32 188000-18ffff 55 32 180000-187fff table 36. bottom boot block addresses, m58wr064kl (continued) bank (1) # size (kword) address range
m58wrxxxku, m58wrxxxkl block address tables 93/123 bank 5 54 32 178000-17ffff 53 32 170000-177fff 52 32 168000-16ffff 51 32 160000-167fff 50 32 158000-15ffff 49 32 150000-157fff 48 32 148000-14ffff 47 32 140000-147fff bank 4 46 32 138000-13ffff 45 32 130000-137fff 44 32 128000-12ffff 43 32 120000-127fff 42 32 118000-11ffff 41 32 110000-117fff 40 32 108000-10ffff 39 32 100000-107fff bank 3 38 32 0f8000-0fffff 37 32 0f0000-0f7fff 36 32 0e8000-0effff 35 32 0e0000-0e7fff 34 32 0d8000-0dffff 33 32 0d0000-0d7fff 32 32 0c8000-0cffff 31 32 0c0000-0c7fff bank 2 30 32 0b8000-0bffff 29 32 0b0000-0b7fff 28 32 0a8000-0affff 27 32 0a0000-0a7fff 26 32 098000-09ffff 25 32 090000-097fff 24 32 088000-08ffff 23 32 080000-087fff table 36. bottom boot block addresses, m58wr064kl (continued) bank (1) # size (kword) address range
block address tables m58wrxxxku, m58wrxxxkl 94/123 bank 1 22 32 078000-07ffff 21 32 070000-077fff 20 32 068000-06ffff 19 32 060000-067fff 18 32 058000-05ffff 17 32 050000-057fff 16 32 048000-04ffff 15 32 040000-047fff parameter bank 14 32 038000-03ffff 13 32 030000-037fff 12 32 028000-02ffff 11 32 020000-027fff 10 32 018000-01ffff 9 32 010000-017fff 8 32 008000-00ffff 7 4 007000-007fff 6 4 006000-006fff 5 4 005000-005fff 4 4 004000-004fff 3 4 003000-003fff 2 4 002000-002fff 1 4 001000-001fff 0 4 000000-000fff 1. there are two bank regions: bank region 2 contains all the banks that are made up of main blocks only; bank region 1 contains the banks that are made up of the parameter and main blocks (parameter bank). table 36. bottom boot block addresses, m58wr064kl (continued) bank (1) # size (kword) address range
m58wrxxxku, m58wrxxxkl common flash interface 95/123 appendix b common flash interface the common flash interface is a jedec approved, standardized data structure that can be read from the flash memory device. it allows a system software to query the device to determine various electrical and timing pa rameters, density information and functions supported by the memory. the system can interface easily with the device, enabling the software to upgrade itself when necessary. when the read cfi query command is issued the device enters cfi query mode and the data structure is read from the memory. tables 37 , 38 , 39 , 40 , 41 , 42 , 43 , 44 , 45 and 46 show the addresses used to retrieve the data. the query data is always presented on the lowest order data outputs (dq0-dq7), the other outputs (dq8-dq15) are set to 0. the cfi data structure also contains a security area where a 64 bit unique security number is written (see figure 6: protection register memory map ). this area can be accessed only in read mode by the final user. it is impossible to change the security number after it has been written by numonyx. issue a read array command to return to read mode. table 37. query structure overview (1) 1. the flash memory display the cfi data structure w hen cfi query command is issued. in this table are listed the main sub-sections detailed in tables 38 , 39 , 40 and 41 . query data is always presented on the lowest order data outputs. offset sub-section name description 00h reserved reserved for algorithm-specific information 10h cfi query identification string command set id and algorithm data offset 1bh system interface information device timing & voltage information 27h device geometry definition flash device layout p primary algorithm-specific extended query table additional information specific to the primary algorithm (optional) a alternate algorithm-specific extended query table additional information specific to the alternate algorithm (optional) 80h security code area lock protection register unique device number and user programmable otp
common flash interface m58wrxxxku, m58wrxxxkl 96/123 table 38. cfi query identification string offset sub-section name description value 00h 0020h manufacturer code numonyx 01h 8823h 8828h 88c0h 8824h 8829h 88c1h device code m58wr016ku m58wr032ku m58wr064ku m58wr016kl m58wr032kl m58wr064kl to p to p to p bottom bottom bottom 02h reserved reserved 03h drc die revision code 04h-0fh reserved reserved 10h 0051h query unique ascii string "qry" "q" 11h 0052h "r" 12h 0059h "y" 13h 0003h primary algorithm command set and control interface id code 16 bit id code defining a specific algorithm 14h 0000h 15h offset = p = 0039h address for primary algorithm extended query table (see ta b l e 4 1 ) p = 39h 16h 0000h 17h 0000h alternate vendor command set and control interface id code second vendor - specified algorithm supported na 18h 0000h 19h value = a = 0000h address for alternate algorithm extended query table na 1ah 0000h
m58wrxxxku, m58wrxxxkl common flash interface 97/123 table 39. cfi query system interface information offset data description value 1bh 0017h v dd logic supply minimum program/erase or write voltage bit 7 to 4 bcd value in volts bit 3 to 0 bcd value in 100 millivolts 1.7 v 1ch 0020h v dd logic supply maximum program/erase or write voltage bit 7 to 4 bcd value in volts bit 3 to 0 bcd value in 100 millivolts 2v 1dh 0085h v pp [programming] supply minimum program/erase voltage bit 7 to 4 hex value in volts bit 3 to 0 bcd value in 100 millivolts 8.5 v 1eh 0095h v pp [programming] supply maximum program/erase voltage bit 7 to 4 hex value in volts bit 3 to 0 bcd value in 100 millivolts 9.5 v 1fh 0004h typical time-out per single byte/word program = 2 n s 16 s 20h 0000h typical time-out for multi-byte program = 2 n s na 21h 000ah typical time-out per individual block erase = 2 n ms 1 s 22h 0000h typical time-out for full chip erase = 2 n ms na 23h 0003h maximum time-out for word program = 2 n times typical 128 s 24h 0000h maximum time-out for multi-byte program = 2 n times typical na 25h 0002h maximum time-out per individual block erase = 2 n times typical 4 s 26h 0000h maximum time-out for chip erase = 2 n times typical na
common flash interface m58wrxxxku, m58wrxxxkl 98/123 table 40. device geometry definition offset word mode data description value 27h 0015h m58wr016ku/l device size = 2 n in number of bytes 2 mbytes 0016h m58wr032ku/l device size = 2 n in number of bytes 4 mbytes 0017h m58wr064ku/l device size = 2 n in number of bytes 8 mbytes 28h 29h 0001h 0000h flash device interface code description x 16 async. 2ah 2bh 0000h 0000h maximum number of bytes in multi-byte program or page = 2 n na 2ch 0002h number of identical sized erase block regions within the device bit 7 to 0 = x = number of erase block regions 2 top devices 2dh 2eh 001eh 0000h m58wr016ku region 1 information number of identical-size erase blocks = 001eh+1 31 003eh 0000h m58wr032ku region 1 information number of identical-size erase blocks = 003eh+1 63 007eh 0000h m58wr064ku region 1 information number of identical-size erase blocks = 007eh+1 127 2fh 30h 0000h 0001h region 1 information block size in region 1 = 0100h * 256 byte 64 kbyte 31h 32h 0007h 0000h region 2 information number of identical-size erase blocks = 0007h+1 8 33h 34h 0020h 0000h region 2 information block size in region 2 = 0020h * 256 byte 8 kbyte 35h 38h reserved for future erase block region information na bottom devices 2dh 2eh 0007h 0000h region 1 information number of identical-size erase block = 0007h+1 8 2fh 30h 0020h 0000h region 1 information block size in region 1 = 0020h * 256 byte 8 kbyte 31h 32h 001eh 0000h m58wr016kl region 1 information number of identical-size erase blocks = 001eh+1 31 003eh 0000h m58wr032kl region 1 information number of identical-size erase blocks = 003eh+1 63 007eh 0000h m58wr064kl region 1 information number of identical-size erase blocks = 007eh+1 127 33h 34h 0000h 0001h region 2 information block size in region 2 = 0100h * 256 byte 64 kbyte 35h 38h reserved for future erase block region information na
m58wrxxxku, m58wrxxxkl common flash interface 99/123 table 41. primary algorithm-specific extended query table (1) offset data description value (p)h = 39h 0050h primary algorithm extended query table unique ascii string ?pri? "p" 0052h "r" 0049h "i" (p+3)h = 3ch 0031h major version number, ascii "1" (p+4)h = 3dh 0033h minor version number, ascii "3" (p+5)h = 3eh 00e6h extended query table contents fo r primary algorithm. address (p+5)h contains less significant byte. bit 0chip erase supported(1 = yes, 0 = no) bit 1erase suspend supported(1 = yes, 0 = no) bit 2program suspend supported(1 = yes, 0 = no) bit 3legacy lock/unlock supported(1 = yes, 0 = no) bit 4queued erase supported(1 = yes, 0 = no) bit 5instant individual block locking supported(1 = yes, 0 = no) bit 6protection bits supported(1 = yes, 0 = no) bit 7page mode read supported(1 = yes, 0 = no) bit 8synchronous read supported(1 = yes, 0 = no) bit 9simultaneous operation supported(1 = yes, 0 = no) bit 10 to 31reserved; undefined bits are ?0?. if bit 31 is ?1? then another 31 bit field of optional features follows at the end of the bit-30 field. no ye s ye s no no ye s ye s ye s ye s ye s 0003h (p+7)h = 40h 0000h (p+8)h = 41h 0000h (p+9)h = 42h 0001h supported functions after suspend read array, read status register and cfi query bit 0program supported after erase suspend (1 = yes, 0 = no) bit 7 to 1reserved; undefined bits are ?0? ye s (p+a)h = 43h 0003h block protect status defines which bits in the block status register section of the query are implemented. bit 0block protect status register lock/unlock bit active(1 = yes, 0 = no) bit 1block lock status register lock-down bit active (1 = yes, 0 = no) bit 15 to 2reserved for future use; undefined bits are ?0? ye s ye s (p+b)h = 44h 0000h (p+c)h = 45h 0018h v dd logic supply optimum program/erase voltage (highest performance) bit 7 to 4hex value in volts bit 3 to 0bcd value in 100 mv 1.8 v (p+d)h = 46h 0090h v pp supply optimum program/erase voltage bit 7 to 4hex value in volts bit 3 to 0bcd value in 100 mv 9v 1. the variable p is a pointer that is defined at cfi offset 15h .
common flash interface m58wrxxxku, m58wrxxxkl 100/123 1. the variable p is a pointer that is defined at cfi offset 15h . 2. bank regions. there are tw o bank regions, see tables 31 , 32 , 33 , 34 , 35 and 36 . table 42. protection register information (1) offset data description value (p+e)h = 47h 0001h number of protection register fields in jedec id space. 0000h indicates that 256 fields are available. 1 (p+f)h = 48h 0080h protection field 1: protection description bits 0-7 lower byte of protection register address bits 8-15 upper byte of protection register address bits 16-23 2 n bytes in factory pre-programmed region bits 24-31 2 n bytes in user programmable region 0080h (p+10)h = 49h 0000h (p+11)h = 4ah 0003h 8 bytes (p+12)h= 4bh 0004h 16 bytes 1. the variable p is a pointer that is defined at cfi offset 15h . table 43. burst read information (1) offset data description value (p+13)h = 4ch 0003h page-mode read capability bits 0-7?n? such that 2 n hex value represents the number of read-page bytes. see offset 28h for device word width to determine page-mode data output width. 8 bytes (p+14)h = 4dh 0004h number of synchronous mode read configuration fields that follow. 4 (p+15)h = 4eh 0001h synchronous mode read capability configuration 1 bit 3-7reserved bit 0-2?n? such that 2 n+1 hex value represents the maximum number of continuous synchronous reads when the device is configured for its maximum word width. a value of 07h indicates that the device is capable of continuous linear bursts that will output data until the internal burst counter reaches the end of the device?s burstable address space. this field?s 3-bit value can be written directly to the read configuration register bit 0-2 if the device is configured for its maximum word width. see offset 28h for word width to determine the burst data output width. 4 (p+16)h = 4fh 0002h synchronous mode read capability configuration 2 8 (p+17)h = 50h 0003h synchronous mode read capability configuration 3 16 (p+18)h = 51h 0007h synchronous mode read capability configuration 4 cont. 1. the variable p is a pointer that is defined at cfi offset 15h . table 44. bank and erase block region information m58wr032ku m58wr032kl description offset data offset data (p+19)h = 52h 02h (p+19)h = 52h 02h number of bank regions within the device
m58wrxxxku, m58wrxxxkl common flash interface 101/123 table 45. bank and erase block region 1 information (1) m58wr016ku, m58wr032ku, m58wr064ku m58wr016kl, m58wr032kl, m58wr064kl description offset data offset data (p+1a)h = 53h 03h (2) 07h (3) 0fh (4) (p+1a)h = 53h 01h number of identical banks within bank region 1 (p+1b)h = 54h 00h (p+1b)h = 54h 00h (p+1c)h = 55h 11h (p+1c)h = 55h 11h number of program or erase operations allowed in bank region 1: bits 0-3: number of simu ltaneous program operations bits 4-7: number of si multaneous erase operations (p+1d)h = 56h 00h (p+1d)h = 56h 00h number of program or erase operations allowed in other banks while a bank in same region is programming bits 0-3: number of simu ltaneous program operations bits 4-7: number of si multaneous erase operations (p+1e)h = 57h 00h (p+1e)h = 57h 00h number of program or erase operations allowed in other banks while a bank in this region is erasing bits 0-3: number of simu ltaneous program operations bits 4-7: number of si multaneous erase operations (p+1f)h = 58h 01h (p+1f)h = 58h 02h types of erase block regions in bank region 1 n = number of erase block regions with contiguous same- size erase blocks. symmetrically blocked banks have one blocking region. (5) (p+20)h = 59h 07h (p+20)h = 59h 07h bank region 1 erase block type 1 information bits 0-15: n+1 = number of identical-sized erase blocks bits 16-31: n256 = number of bytes in erase block region (p+21)h = 5ah 00h (p+21)h = 5ah 00h (p+22)h = 5bh 00h (p+22)h = 5bh 20h (p+23)h = 5ch 01h (p+23)h = 5ch 00h (p+24)h = 5dh 64h (p+24)h = 5dh 64h bank region 1 (erase block type 1) minimum block erase cycles 1000 (p+25)h = 5eh 00h (p+25)h = 5eh 00h (p+26)h = 5fh 01h (p+26)h = 5fh 01h bank region 1 (erase block type 1): bits per cell, internal ecc bits 0-3: bits per cell in erase region bit 4: reserved for ?internal ecc used? bits 5-7: reserved 5eh 01 5eh 01 (p+27)h = 60h 03h (p+27)h = 60h 03h bank region 1 (erase block type 1): page mode and synchronous mode capabilities bit 0: page-mode reads permitted bit 1: synchronous reads permitted bit 2: synchronous writes permitted bits 3-7: reserved
common flash interface m58wrxxxku, m58wrxxxkl 102/123 (p+28)h = 61h 06h bank region 1 erase block type 2 information bits 0-15: n+1 = number of identical-sized erase blocks bits 16-31: n256 = number of bytes in erase block region (p+29)h = 62h 00h (p+2a)h = 63h 00h (p+2b)h = 64h 01h (p+2c)h = 65h 64h bank region 1 (erase block type 2) minimum block erase cycles 1000 (p+2d)h = 66h 00h (p+2e)h = 67h 01h bank regions 1 (erase block type 2): bits per cell, internal ecc bits 0-3: bits per cell in erase region bit 4: reserved for ?internal ecc used? bits 5-7: reserved (p+2f)h = 68h 03h bank region 1 (erase block type 2): page mode and synchronous mode capabilities bit 0: page-mode reads permitted bit 1: synchronous reads permitted bit 2: synchronous writes permitted bits 3-7: reserved 1. the variable p is a pointer that is defined at cfi offset 15h . 2. applies to m58wr016ku. 3. applies to m58wr032ku. 4. applies to m58wr064ku. 5. bank regions. there are tw o bank regions, see tables 31 , 32 , 33 , 34 , 35 and 36 . table 45. bank and erase block region 1 information (1) (continued) m58wr016ku, m58wr032ku, m58wr064ku m58wr016kl, m58wr032kl, m58wr064kl description offset data offset data
m58wrxxxku, m58wrxxxkl common flash interface 103/123 table 46. bank and erase block region 2 information (1) m58wr016ku, m58wr032ku, m58wr064ku m58wr016kl, m58wr032kl, m58wr064kl description offset data offset data (p+28)h = 61h 01h (p+30)h = 69h 03h (2) 07h (3) 0fh (4) number of identical banks within bank region 2 (p+29)h = 62h 00h (p+31)h = 6ah 00h (p+2a)h = 63h 11h (p+32)h = 6bh 11h number of program or erase operations allowed in bank region 2: bits 0-3: number of simultaneous program operations bits 4-7: number of simultaneous erase operations (p+2b)h = 64h 00h (p+33)h = 6ch 00h number of program or erase operations allowed in other banks while a bank in this region is programming bits 0-3: number of simultaneous program operations bits 4-7: number of simultaneous erase operations (p+2c)h = 65h 00h (p+34)h = 6dh 00h number of program or erase operations allowed in other banks while a bank in this region is erasing bits 0-3: number of simultaneous program operations bits 4-7: number of simultaneous erase operations (p+2d)h = 66h 02h (p+35)h = 6eh 01h types of erase block regions in bank region 2 n = number of erase block regions with contiguous same-size erase blocks. symmetrically blocked banks have one blocking region. (5) (p+2e)h = 67h 06h (p+36)h = 6fh 07h bank region 2 erase block type 1 information bits 0-15: n+1 = number of identical-sized erase blocks bits 16-31: n256 = number of bytes in erase block region (p+2f)h = 68h 00h (p+37)h = 70h 00h (p+30)h = 69h 00h (p+38)h = 71h 00h (p+31)h = 6ah 01h (p+39)h = 72h 01h (p+32)h = 6bh 64h (p+3a)h = 73h 64h bank region 2 (erase block type 1) minimum block erase cycles 1000 (p+33)h = 6ch 00h (p+3b)h = 74h 00h (p+34)h = 6dh 01h (p+3c)h = 75h 01h bank region 2 (erase block type 1): bits per cell, internal ecc bits 0-3: bits per cell in erase region bit 4: reserved for ?internal ecc used? bits 5-7: reserved (p+35)h = 6eh 03h (p+3d)h = 76h 03h bank region 2 (erase block type 1): page mode and synchronous mode capabilities (defined in ta bl e 4 3 ) bit 0: page-mode reads permitted bit 1: synchronous reads permitted bit 2: synchronous writes permitted bits 3-7: reserved
common flash interface m58wrxxxku, m58wrxxxkl 104/123 (p+36)h = 6fh 07h bank region 2 erase block type 2 information bits 0-15: n+1 = number of identical-sized erase blocks bits 16-31: n256 = number of bytes in erase block region (p+37)h = 70h 00h (p+38)h = 71h 20h (p+39)h = 72h 00h (p+3a)h = 73h 64h bank region 2 (erase block type 2) minimum block erase cycles 1000 (p+3b)h = 74h 00h (p+3c)h = 75h 01h bank region 2 (erase block type 2): bits per cell, internal ecc bits 0-3: bits per cell in erase region bit 4: reserved for ?internal ecc used? bits 5-7: reserved (p+3d)h = 76h 03h bank region 2 (erase block type 2): page mode and synchronous mode capabilities (defined in ta bl e 4 3 ) bit 0: page-mode reads permitted bit 1: synchronous reads permitted bit 2: synchronous writes permitted bits 3-7: reserved (p+3e)h = 77h (p+3e)h = 77h feature space definitions (p+3f)h = 78h (p+3f)h = 78h reserved 1. the variable p is a pointer that is defined at cfi offset 15h . 2. applies to m58wr016kl. 3. applies to m58wr032kl. 4. applies to m58wr064kl. 5. bank regions. there are tw o bank regions, see tables 31 , 32 , 33 , 34 , 35 and 36 . table 46. bank and erase block region 2 information (1) (continued) m58wr016ku, m58wr032ku, m58wr064ku m58wr016kl, m58wr032kl, m58wr064kl description offset data offset data
m58wrxxxku, m58wrxxxkl flowcharts and pseudocodes 105/123 appendix c flowcharts and pseudocodes figure 20. program flowchart and pseudocode 1. status check of sr1 (protected block), sr3 (v pp invalid) and sr4 (program erro r) can be made after each program operation or after a sequence. 2. if an error is found, the status register must be cl eared before further program/er ase controller operations. 3. any address within the bank can equally be used. write 40h or 10h (3) ai06170c start write address & data read status register (3) yes no sr7 = 1 yes no sr3 = 0 no sr4 = 0 v pp invalid error (1, 2) program error (1, 2) program_command (addresstoprogram, datatoprogram) {: writetoflash (addresstoprogram, 0x40); /*writetoflash (addresstoprogram, 0x10);*/ /*see note (3)*/ do { status_register=readflash (addresstoprogram); "see note (3)"; /* e or g must be toggled*/ } while (status_register.sr7== 0) ; if (status_register.sr3==1) /*v pp invalid error */ error_handler ( ) ; yes end yes no sr1 = 0 program to protected block error (1, 2) writetoflash (addresstoprogram, datatoprogram) ; /*memory enters read status state after the program command*/ if (status_register.sr4==1) /*program error */ error_handler ( ) ; if (status_register.sr1==1) /*program to protect block error */ error_handler ( ) ; }
flowcharts and pseudocodes m58wrxxxku, m58wrxxxkl 106/123 figure 21. double word program flowchart and pseudocode 1. status check of b1 (protected block), b3 (v pp invalid) and b4 (program error) c an be made after each program operation or after a sequence. 2. if an error is found, the status register must be cleared before further program/erase operations. 3. address 1 and address 2 mu st be consecutive addresses differing only for bit a0. 4. any address within the bank can equally be used. write 35h ai06171b start write address 1 & data 1 (3, 4) read status register (4) yes no sr7 = 1 yes no sr3 = 0 no sr4 = 0 v pp invalid error (1, 2) program error (1, 2) yes end yes no sr1 = 0 program to protected block error (1, 2) write address 2 & data 2 (3) double_word_program_command (addresstoprogram1, datatoprogram1, addresstoprogram2, datatoprogram2) { writetoflash (addresstoprogram1, 0x35); /*see note (4)*/ writetoflash (addresstoprogram1, datatoprogram1) ; /*see note (3) */ writetoflash (addresstoprogram2, datatoprogram2) ; /*see note (3) */ /*memory enters read status state after the program command*/ do { status_register=readflash (addresstoprogram) ; "see note (4)" /* e or g must be toggled*/ } while (status_register.sr7== 0) ; if (status_register.sr3==1) /*v pp invalid error */ error_handler ( ) ; if (status_register.sr4==1) /*program error */ error_handler ( ) ; if (status_register.sr1==1) /*program to protect block error */ error_handler ( ) ; }
m58wrxxxku, m58wrxxxkl flowcharts and pseudocodes 107/123 figure 22. quadruple word program flowchart and pseudocode 1. status check of sr1 (protected block), sr3 (v pp invalid) and sr4 (program erro r) can be made after each program operation or after a sequence. 2. if an error is found, the status register must be cleared before further program/erase operations. 3. address 1 to address 4 must be consecutive addresses differi ng only for bits a0 and a1. 4. any address within the bank can equally be used. write 56h ai06977b start write address 1 & data 1 (3, 4) read status register (4) yes no sr7 = 1 yes no sr3 = 0 no sr4 = 0 v pp invalid error (1, 2) program error (1, 2) yes end yes no sr1 = 0 program to protected block error (1, 2) write address 2 & data 2 (3) quadruple_word_program_command (addresstoprogram1, datatoprogram1, addresstoprogram2, datatoprogram2, addresstoprogram3, datatoprogram3, addresstoprogram4, datatoprogram4) { writetoflash (addresstoprogram1, 0x56); /*see note (4) */ writetoflash (addresstoprogram1, datatoprogram1) ; /*see note (3) */ writetoflash (addresstoprogram2, datatoprogram2) ; /*see note (3) */ writetoflash (addresstoprogram3, datatoprogram3) ; /*see note (3) */ writetoflash (addresstoprogram4, datatoprogram4) ; /*see note (3) */ /*memory enters read status state after the program command*/ do { status_register=readflash (addresstoprogram) ; /"see note (4) "/ /* e or g must be toggled*/ } while (status_register.sr7== 0) ; if (status_register.sr3==1) /*v pp invalid error */ error_handler ( ) ; if (status_register.sr4==1) /*program error */ error_handler ( ) ; if (status_register.sr==1) /*program to protect block error */ error_handler ( ) ; } write address 3 & data 3 (3) write address 4 & data 4 (3)
flowcharts and pseudocodes m58wrxxxku, m58wrxxxkl 108/123 figure 23. program suspend & resume flowchart and pseudocode 1. the read status register command (write 70h) can be issu ed just before or just after the program resume command. write 70h ai10117b read status register yes no sr7 = 1 yes no sr2 = 1 write d0h read data from another address start write b0h program complete write ffh program_suspend_command ( ) { writetoflash (any_address, 0xb0) ; writetoflash (bank_address, 0x70) ; /* read status register to check if program has already completed */ do { status_register=readflash (bank_address) ; /* e or g must be toggled*/ } while (status_register.sr7== 0) ; if (status_register.sr2==0) /*program completed */ { writetoflash (bank_address, 0xff) ; read_data ( ) ; /*the device returns to read array (as if program/erase suspend was not issued).*/ } else { writetoflash (bank_address, 0xff) ; read_data ( ); /*read data from another address*/ writetoflash (any_address, 0xd0) ; /*write 0xd0 to resume program*/ writetoflash (bank_address, 0x70) ; /*read status register to check if program has completed */ } } write ffh program continues with bank in read status register mode read data write 70h (1)
m58wrxxxku, m58wrxxxkl flowcharts and pseudocodes 109/123 figure 24. block erase flowchart and pseudocode 1. if an error is found, the status register must be cleared before further program/erase operations. 2. any address within the bank can equally be used. 3. amax is equal to a19 in the m58wr016ku/l, to a20 in the m58wr032ku/l, and to a21 in the m58wr064ku/l. write 20h (2) ai13531 start write block address & d0h read status register (2) yes no sr7 = 1 yes no sr3 = 0 yes sr4, sr5 = 1 v pp invalid error (1) command sequence error (1) no no sr5 = 0 erase error (1) end yes no sr1 = 0 erase to protected block error (1) yes erase_command ( blocktoerase ) { writetoflash (blocktoerase, 0x20) ; /*see note (2) */ writetoflash (blocktoerase, 0xd0) ; /* only adq12-adq15 and a16-amax (3) are significant */ /* memory enters read status state after the erase command */ } while (status_register.sr7== 0) ; do { status_register=readflash (blocktoerase) ; /* see note (2) */ /* e or g must be toggled*/ if (status_register.sr3==1) /*v pp invalid error */ error_handler ( ) ; if ( (status_register.sr4==1) && (status_register.sr5==1) ) /* command sequence error */ error_handler ( ) ; if (status_register.sr1==1) /*program to protect block error */ error_handler ( ) ; if ( (status_register.sr5==1) ) /* erase error */ error_handler ( ) ; }
flowcharts and pseudocodes m58wrxxxku, m58wrxxxkl 110/123 figure 25. erase suspend & resume flowchart and pseudocode 1. the read status register command (write 70h) can be is sued just before or just after the erase resume command. write 70h ai13530b read status register yes no sr7 = 1 yes no sr6 = 1 erase continues with bank in read status register mode write d0h read data from another block, program, set configuration register or block lock/unlock/lock-down start write b0h erase complete write ffh read data write ffh erase_suspend_command ( ) { writetoflash (bank_address, 0xb0) ; writetoflash (bank_address, 0x70) ; /* read status register to check if erase has already completed */ do { status_register=readflash (bank_address) ; /* e or g must be toggled*/ } while (status_register.sr7== 0) ; if (status_register.sr6==0) /*erase completed */ { writetoflash (bank_address, 0xff) ; read_data ( ) ; /*the device returns to read array (as if program/erase suspend was not issued).*/ } else { writetoflash (bank_address, 0xff) ; read_program_data ( ); /*read or program data from another block*/ writetoflash (bank_address, 0xd0) ; /*write 0xd0 to resume erase*/ writetoflash (bank_address, 0x70) ; /*read status register to check if erase has completed */ } } write 70h (1)
m58wrxxxku, m58wrxxxkl flowcharts and pseudocodes 111/123 figure 26. locking operations flowchart and pseudocode 1. any address within the bank can equally be used. write 01h, d0h or 2fh ai06176b read block lock states yes no locking change confirmed? start write 60h (1) locking_operation_command (address, lock_operation) { writetoflash (address, 0x60) ; /*configuration setup*/ /* see note (1) */ if (readflash (address) ! = locking_state_expected) error_handler () ; /*check the locking state (see read block signature table )*/ writetoflash (address, 0xff) ; /*reset to read array mode*/ /*see note (1) */ } write ffh (1) write 90h (1) end if (lock_operation==lock) /*to protect the block*/ writetoflash (address, 0x01) ; else if (lock_operation==unlock) /*to unprotect the block*/ writetoflash (address, 0xd0) ; else if (lock_operation==lock-down) /*to lock the block*/ writetoflash (address, 0x2f) ; writetoflash (address, 0x90) ; /*see note (1) */
flowcharts and pseudocodes m58wrxxxku, m58wrxxxkl 112/123 figure 27. protection register program flowchart and pseudocode 1. status check of sr1 (protected block), sr3 (v pp invalid) and sr4 (program erro r) can be made after each program operation or after a sequence. 2. if an error is found, the status register must be cl eared before further program/er ase controller operations. 3. any address within the bank can equally be used. write c0h (3) ai06177b start write address & data read status register (3) yes no sr7 = 1 yes no sr3 = 0 no sr4 = 0 v pp invalid error (1, 2) program error (1, 2) protection_register_program_command (addresstoprogram, datatoprogram) {: writetoflash (addresstoprogram, 0xc0) ; /*see note (3) */ do { status_register=readflash (addresstoprogram) ; /* see note (3) */ /* e or g must be toggled*/ } while (status_register.sr7== 0) ; if (status_register.sr3==1) /*vpp invalid error */ error_handler ( ) ; yes end yes no sr1 = 0 program to protected block error (1, 2) writetoflash (addresstoprogram, datatoprogram) ; /*memory enters read status state after the program command*/ if (status_register.sr4==1) /*program error */ error_handler ( ) ; if (status_register.sr1==1) /*program to protect block error */ error_handler ( ) ; }
m58wrxxxku, m58wrxxxkl flowcharts and pseudocodes 113/123 figure 28. enhanced factory program flowchart 1. address can remain starting address wa1 or be incremented. write 30h address wa1 ai06160 start read status register yes no sr0 = 0? end write d0h address wa1 write pd1 address wa1 write pd2 address wa2 ( 1) yes no read status register write pdn address wan ( 1) yes no read status register read status register no write pd1 address wa1 ( 1) write pdn address wan ( 1) no read status register write ffffh address block wa1 setup phase verify phase sr0 = 0? sr0 = 0? sr0 = 0? sr0 = 0? read status register yes no sr0 = 0? write ffffh address block wa1 sr7 = 0? yes no check sr4, sr3 and sr1 for program, v pp and lock errors exit read status register no write pd2 address wa2 ( 1) sr0 = 0? yes read status register sr7 = 1? check status register for errors yes no yes yes program phase exit phase = / / =
flowcharts and pseudocodes m58wrxxxku, m58wrxxxkl 114/123 16.1 enhanced factory program pseudocode efp_command(addressflow,dataflow,n) /* n is the number of data to be programmed */ { /* setup phase */ writetoflash(addressflow[0],0x30); writetoflash(addressflow[0],0xd0); status_register=readflash(any_address); if (status_register.sr7==1){ /*efp aborted for an error*/ if (status_register.sr4==1) /*program error*/ error_handler(); if (status_register.sr3==1) /*vpp invalid error*/ error_handler(); if (status_register.sr1==1) /*program to protect block error*/ error_handler(); } else{ /*program phase*/ do{ status_register=readflash(any_address); /* e or g must be toggled*/ } while (status_register.sr0==1) /*ready for first data*/ for (i=0; i++; i< n){ writetoflash(addressflow[i],dataflow[i]); /* status register polling*/ do{ status_register=readflash(any_address); /* e or g must be toggled*/ } while (status_register.sr0==1); /* ready for a new data */ } writetoflash(another_block_address,ffffh); /* verify phase */ for (i=0; i++; i< n){ writetoflash(addressflow[i],dataflow[i]); /* status register polling*/ do{ status_register=readflash(any_address); /* e or g must be toggled*/ } while (status_register.sr0==1); /* ready for a new data */ } writetoflash(another_block_address,ffffh); /* exit program phase */ /* exit phase */ /* status register polling */ do{ status_register=readflash(any_address); /* e or g must be toggled */ } while (status_register.sr7==0); if (status_register.sr4==1) /*program failure error*/ error_handler(); if (status_register.sr3==1) /*vpp invalid error*/ error_handler(); if (status_register.sr1==1) /*program to protect block error*/ error_handler(); } }
m58wrxxxku, m58wrxxxkl flowcharts and pseudocodes 115/123 figure 29. quadruple enhanced factory program flowchart 1. address can remain starting address wa1 (in which case th e next page is programmed) or can be any address in the same block. 2. the address is only checked for the first word of each page as the order to program the words is fixed, so subsequent words in each page can be written to any address. write 75h address wa1 ai06178b start end write pd1 address wa1 ( 1) write pd2 address wa2 ( 2) write pd3 address wa3 ( 2) read status register setup phase program and verify phase sr7 = 0? yes no check sr4, sr3 and sr1 for program, v pp and lock errors exit check sr4 for programming errors yes load phase exit phase write pd4 address wa4 ( 2) sr0 = 0? last page? yes no write ffffh address block wa1 write pd1 address wa1 read status register no first load phase = /
flowcharts and pseudocodes m58wrxxxku, m58wrxxxkl 116/123 16.2 quadruple enhanced factory program pseudocode quad_efp_command(addressflow,dataflow,n) /* n is the number of pages to be programmed.*/ { /* setup phase */ writetoflash(addressflow[0],0x75); for (i=0; i++; i< n){ /*data load phase*/ /*first data*/ writetoflash(addressflow[i],dataflow[i,0]); /*at the first data of the first page, quad-efp may be aborted*/ if (first_page) { status_register=readflash(any_address); if (status_register.sr7==1){ /*efp aborted for an error*/ if (status_register.sr4==1) /*program error*/ error_handler(); if (status_register.sr3==1) /*vpp invalid error*/ error_handler(); if (status_register.sr1==1) /*program to protect block error*/ error_handler(); } } /*2nd data*/ writetoflash(addressflow[i],dataflow[i,1]); /*3rd data*/ writetoflash(addressflow[i],dataflow[i,2]); /*4th data*/ writetoflash(addressflow[i],dataflow[i,3]); /* program&verify phase */ do{ status_register=readflash(any_address); /* e or g must be toggled*/ }while (status_register.sr0==1) } /* exit phase */ writetoflash(another_block_address,ffffh); /* status register polling */ do{ status_register=readflash(any_address); /* e or g must be toggled */ } while (status_register.sr7==0); if (status_register.sr1==1) /*program to protected block error*/ error_handler(); if (status_register.sr3==1) /*vpp invalid error*/ error_handler(); if (status_register.sr4==1) /*program failure error*/ error_handler(); } }
m58wrxxxku, m58wrxxxkl command interface state tables 117/123 appendix d command interface state tables table 47. command interface states - modify table, next state (1) current ci state command input read array (2) (ffh) wp setup (3)(4) (10/40h) dwp, qwp setup (3)(4) (35h, 56h) block erase setup (3)(4) (20h) efp setup (30h) quad-efp setup (75h) erase confirm, p/e resume, block unlock confirm, efp confirm (d0h) program/ erase suspend (b0h) read status register (70h) clear status register (5) (50h) read electronic signature, read cfi query (90h, 98h) ready ready program setup program setup erase setup efp setup quad-efp setup ready lock/cr setup ready (lock error) ready ready (lock error) otp setup otp busy busy otp busy is in otp busy otp busy is in otp busy otp busy program setup program busy busy program busy is in program busy program busy ps program busy is in program busy program busy suspend ps is in program suspend program busy program suspend is in ps program suspend erase setup ready (error) erase busy ready (error) busy erase busy is in erase busy erase busy es erase busy is in erase busy erase busy suspend es program in es is in erase suspend erase busy erase suspend is in es erase suspend program in es setup program busy in erase suspend busy program busy in es is in program busy in erase suspend program busy in es ps in es program busy in erase suspend is in program busy in es program busy in erase suspend suspend ps in es is in program suspend in es program busy in es program suspend in erase suspend is in ps in es program suspend in erase suspend lock/cr setup in es erase suspend (lock error) es erase suspend (lock error)
command interface state tables m58wrxxxku, m58wrxxxkl 118/123 efp setup ready (error) efp busy ready (error) busy efp busy (6) verify efp verify (6) quad efp setup quad efp busy (6) busy quad efp busy (6) 1. ci = command interface, cr = configuration register , efp = enhanced factory progr am, quad efp = quadruple enhanced factory program, dwp = double word program, qwp = quadruple word program, p/e. c. = program/erase controller, ps = program suspend, es = erase suspend, is = illegal state. 2. at power-up, all banks are in read array mode. a read array command issued to a busy bank, results in undetermined data output. 3. the two cycle command should be issued to the same bank address. 4. if the p/e.c. is active , both cycles are ignored. 5. the clear status register command clears the status regist er error bits except when t he p/e.c. is busy or suspended. 6. efp and quad efp are allowed only when status register bit sr0 is set to ?0?.efp and quad efp are busy if block address is first efp address. an y other commands are treated as data. table 47. command interface states - modify table, next state (1) (continued) current ci state command input read array (2) (ffh) wp setup (3)(4) (10/40h) dwp, qwp setup (3)(4) (35h, 56h) block erase setup (3)(4) (20h) efp setup (30h) quad-efp setup (75h) erase confirm, p/e resume, block unlock confirm, efp confirm (d0h) program/ erase suspend (b0h) read status register (70h) clear status register (5) (50h) read electronic signature, read cfi query (90h, 98h)
m58wrxxxku, m58wrxxxkl command interface state tables 119/123 table 48. command interface states - modify table, next output (1) current ci state command input (2) read array (3) (ffh) dwp, qwp setup (4)(5) (35h, 56h) block erase setup (4)(5) (20h) efp setup (30h) quad- efp setup (75h) erase confirm p/e resume, block unlock confirm, efp confirm (d0h) program/ erase suspend (b0h) read status register (70h) clear status register (6) (50h) read electronic signature, read cfi query (90h, 98h) program setup status register erase setup otp setup program setup in erase suspend efp setup efp busy efp verify quad efp setup quad efp busy lock/cr setup lock/cr setup in erase suspend otp busy array status register output unchanged status register output unchanged status register ready electronic signature/cfi program busy erase busy program/erase suspend program busy in erase suspend program suspend in erase suspend illegal state output unchanged 1. ci = command interface, cr = configuration register , efp = enhanced factory progr am, quad efp = quadruple enhanced factory program, dwp = double word program, qwp = quadruple word program, p/e. c. = program/erase controller, is = illegal state, es = erase suspend, ps = program suspend. 2. the output state shows the type of data that appears at the outputs if the bank address is the same as the command address. a bank can be placed in read array, read status r egister, read electronic signat ure or read cfi query mode, depending on the command issued. each bank remains in its la st output state until a new command is issued. the next state does not depend on the bank?s output state. 3. at power-up, all banks are in read array mode. a read array command issued to a busy bank, results in undetermined data output. 4. the two cycle command should be issued to the same bank address. 5. if the p/e.c. is active , both cycles are ignored. 6. the clear status register command clears the status regist er error bits except when t he p/e.c. is busy or suspended.
command interface state tables m58wrxxxku, m58wrxxxkl 120/123 table 49. command interface states - lock table, next state (1) current ci state command input lock/cr setup (2) (60h) otp setup (2) (c0h) block lock confirm (01h) block lock- down confirm (2fh) set cr confirm (03h) efp exit, quad efp exit (3) illegal command (4) p/e. c. operation completed ready lock/cr setup otp setup ready n/a lock/cr setup ready (lock error) ready ready (lock error) n/a otp setup otp busy busy is in otp busy otp busy ready is in otp busy otp busy is ready program setup program busy n/a busy is in program busy program busy ready is in program busy program busy is ready suspend is in ps program suspend n/a is in ps program suspend n/a erase setup ready (error) n/a busy is in erase busy erase busy ready is in erase busy erase busy is ready suspend lock/cr setup in es is in erase suspend erase suspend n/a is in es erase suspend n/a program in erase suspend setup program busy in erase suspend busy is in program busy in es program busy in erase suspend es is in program busy in es program busy in es is in es suspend is in ps in es program suspend in erase suspend n/a is in ps in es program suspend in erase suspend lock/cr setup in es erase suspend (lock error) erase suspend erase suspend (lock error) n/a efp setup ready (error) n/a busy efp busy (5) efp verify efp busy (5) n/a verify efp verify (5) ready efp verify (5) ready quadefp setup quad efp busy (5) n/a busy quad efp busy (5) ready quad efp busy (4) ready 1. ci = command interface, cr = configuration register , efp = enhanced factory progr am, quad efp = quadruple enhanced factory program, p/e. c. = program/erase controller , is = illegal state, es = erase suspend, ps = program suspend. 2. if the p/e.c. is active , both cycles are ignored. 3. efp and quad efp exit when block address is diffe rent from first block address and data is ffffh. 4. illegal commands are those not defined in the command set. 5. efp and quad efp are allowed only when status register bi t sr0 is set to ?0?. efp and quad efp are busy if block address is first efp address. an y other commands are treated as data.
m58wrxxxku, m58wrxxxkl command interface state tables 121/123 table 50. command interface states - lock table, next output (1) current ci state command input lock/cr setup (2) (60h) otp setup (2) (c0h) block lock confirm (01h) block lock- down confirm (2fh) set cr confirm (03h) efp exit, quad efp exit (3) illegal command (4) p/e. c. operation completed program setup status register output unchanged erase setup otp setup program setup in erase suspend efp setup efp busy efp verify quad efp setup quad efp busy lock/cr setup status register array status register lock/cr setup in erase suspend otp busy status register output unchanged array output unchanged ready program busy erase busy program/erase suspend program busy in erase suspend program suspend in erase suspend illegal state output unchanged 1. ci = command interface, cr = configuration register , efp = enhanced factory progr am, quad efp = quadruple enhanced factory program, p/e. c. = program/erase controller. 2. if the p/e.c. is active , both cycles are ignored. 3. efp and quad efp exit when block address is diffe rent from first block address and data is ffffh. 4. illegal commands are those not defined in the command set.
revision history m58wrxxxku, m58wrxxxkl 122/123 revision history table 51. document revision history date version changes 06-nov-2006 0.1 initial release. m58wr032ku/l (revision 0.2 of 21-jul-2006) and m58wr064ku/l (revision 0.1 of 21-sep-2006) datasheets merged. m58wr016ku and m58wr016kl part numbers added. changes made: document status promoted from target specification to preliminary data. 60 ns speed class and 86 mhz frequency added. during erase suspend, the set configuration register command is also accepted (see program/erase suspend command and figure 23: program suspend & resume flowchart and pseudocode ). v ddq max modified in table 19: absolute maximum ratings . v pplk max modified in table 23: dc characteristics - voltages . data and values modified at address offsets 1dh and 1eh in ta b l e 3 9 : cfi query system inte rface information . value modified at address offset (p+d)h = 46h in table 41: primary algorithm-specific extended query table . data modified at address offs ets (p+2e)h = 67h, (p+30)h = 69h and (p+31)h = 6ah in table 46: bank and erase block region 2 information . appendix d: command interface state tables updated. 05-jan-2007 0.2 parameter block, main block and bank program values modified for v pp = v pph in table 18: program, erase times and endurance cycles . v rph removed from table 23: dc characteristics - voltages . t eltv , t ehtz , t ehqz , t ghqz , t avlh , t ellh , t lhax , t lhgl modified for 60 ns speed class in table 24: asynchronous read ac characteristics . t avkh , t elkh , t eltv , t ehel , t ghtv , t ghtl , t khax , t khqx , t khtx , t llkh modified for 60 ns speed class in table 25: synchronous read ac characteristics . t vdhph modified in table 28: reset and power-up ac characteristics . data modified at address offset (p+d)h = 46h in table 41: primary algorithm-specific extended query table . small text changes. 16-jan-2007 0.3 small text changes. section 5.8: program/erase suspend command and figure 25: erase suspend & resume flowchart and pseudocode ) updated. i dd5 values when v pp = v dd and i dd6 values modified in table 22: dc characteristics - currents . note 1 added below ta bl e 4 1 , note 1 added below ta b l e 4 2 and note 1 added below ta bl e 4 3 . t avlh min, t ellh min, t lhax min, t lhgl min and max values modified in table 26: write ac characteristics, write enable controlled and table 27: write ac characteristics, chip enable controlled . 25-may-2007 1 document status promoted from pr eliminary data to full datasheet. i dd1 , i dd5 and i dd6 changed in table 22.: dc characteristics - currents . data modified in table 46.: bank and erase block region 2 information . 3-dec-2007 2 applied numonyx branding.
m58wrxxxku, m58wrxxxkl 123/123 please read carefully: information in this document is provided in connection with numonyx? products. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. except as provided in numonyx's terms and conditions of sale for such products, numonyx assumes no liability whatsoever, and numonyx disclaims any express or implied warranty, relating to sale and/or use of numonyx products including liability or warranties re lating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. numonyx products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in n uclear facility applications. numonyx may make changes to specifications and product descriptions at any time, without notice. numonyx, b.v. may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights th at relate to the presented subject matter. the furnishing of documents and other materials and information does not provide any license, express or implied, by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights. designers must not rely on the absence or characteristics of any features or instructions marked ?reserved? or ?undefined.? num onyx reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. contact your local numonyx sales office or your distributor to obtain the latest specifications and before placing your product order. copies of documents which have an order number and are referenced in this document, or other numonyx literature may be obtained by visiting numonyx's website at http://www.numonyx.com . numonyx strataflash is a trademark or registered trademark of numonyx or its subsidiaries in the united states and other countr ies. *other names and brands may be claimed as the property of others. copyright ? 11/5/7, numonyx, b.v., all rights reserved.

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